Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1453

1

T12

13

T13

2

T19

40

auto[1]

1424

1

T12

5

T13

4

T19

32

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

747

1

T17

21

T60

19

T61

1

auto[1]

2130

1

T12

18

T13

6

T19

72

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2566

1

T12

18

T13

6

T19

72

auto[1]

311

1

T17

7

T60

8

T61

1

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	513	1			T12	2		T13	1		T19	16
valid[1]	603	1			T12	4		T13	1		T19	16
valid[2]	569	1			T12	5		T13	1		T19	9
valid[3]	589	1			T12	4		T13	1		T19	16
valid[4]	603	1			T12	3		T13	2		T19	15

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	37	1			T17	1		T62	3		T111	1
auto[0]	auto[0]	valid[0]	auto[1]	198	1			T12	1		T19	11		T23	6
auto[0]	auto[0]	valid[1]	auto[0]	43	1			T60	1		T111	2		T384	2
auto[0]	auto[0]	valid[1]	auto[1]	234	1			T12	4		T19	8		T20	2
auto[0]	auto[0]	valid[2]	auto[0]	53	1			T17	4		T60	2		T62	4
auto[0]	auto[0]	valid[2]	auto[1]	212	1			T12	3		T13	1		T19	3
auto[0]	auto[0]	valid[3]	auto[0]	38	1			T60	1		T62	2		T385	1
auto[0]	auto[0]	valid[3]	auto[1]	210	1			T12	3		T19	8		T23	2
auto[0]	auto[0]	valid[4]	auto[0]	52	1			T17	2		T60	1		T111	1
auto[0]	auto[0]	valid[4]	auto[1]	217	1			T12	2		T13	1		T19	10
auto[0]	auto[1]	valid[0]	auto[0]	37	1			T17	4		T71	1		T380	3
auto[0]	auto[1]	valid[0]	auto[1]	177	1			T12	1		T13	1		T19	5
auto[0]	auto[1]	valid[1]	auto[0]	51	1			T17	1		T62	2		T71	2
auto[0]	auto[1]	valid[1]	auto[1]	215	1			T13	1		T19	8		T20	1
auto[0]	auto[1]	valid[2]	auto[0]	42	1			T17	1		T60	4		T62	1
auto[0]	auto[1]	valid[2]	auto[1]	186	1			T12	2		T19	6		T21	1
auto[0]	auto[1]	valid[3]	auto[0]	39	1			T60	2		T111	1		T384	2
auto[0]	auto[1]	valid[3]	auto[1]	244	1			T12	1		T13	1		T19	8
auto[0]	auto[1]	valid[4]	auto[0]	44	1			T17	1		T62	2		T111	1
auto[0]	auto[1]	valid[4]	auto[1]	237	1			T12	1		T13	1		T19	5
auto[1]	auto[0]	valid[0]	auto[0]	30	1			T17	1		T62	1		T72	1
auto[1]	auto[0]	valid[1]	auto[0]	30	1			T17	1		T62	1		T71	1
auto[1]	auto[0]	valid[2]	auto[0]	47	1			T60	1		T62	2		T71	1
auto[1]	auto[0]	valid[3]	auto[0]	25	1			T17	1		T62	1		T111	2
auto[1]	auto[0]	valid[4]	auto[0]	27	1			T60	4		T62	1		T71	1
auto[1]	auto[1]	valid[0]	auto[0]	34	1			T71	1		T111	5		T380	1
auto[1]	auto[1]	valid[1]	auto[0]	30	1			T17	1		T60	1		T62	1
auto[1]	auto[1]	valid[2]	auto[0]	29	1			T17	2		T61	1		T62	2
auto[1]	auto[1]	valid[3]	auto[0]	33	1			T60	2		T111	1		T384	1
auto[1]	auto[1]	valid[4]	auto[0]	26	1			T17	1		T62	2		T388	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal