Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17236

1

T15

8

T17

498

T18

6

auto[1]

19614

1

T12

18

T13

79

T19

660

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30473

1

T12

18

T13

79

T19

660

auto[1]

6377

1

T15

4

T17

175

T18

3

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	19114	1			T12	18		T13	38		T19	347
others[1]	3112	1			T13	9		T19	57		T17	39
others[2]	3077	1			T13	7		T19	47		T15	1
others[3]	3505	1			T13	12		T19	74		T15	5
interest[1]	1972	1			T13	4		T19	25		T17	32
interest[4]	12597	1			T12	18		T13	23		T19	216
interest[64]	6070	1			T13	9		T19	110		T15	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	5508	1			T15	1		T17	168		T18	2
auto[0]	auto[0]	others[1]	946	1			T17	24		T18	1		T60	26
auto[0]	auto[0]	others[2]	937	1			T17	28		T60	29		T61	2
auto[0]	auto[0]	others[3]	1049	1			T15	3		T17	31		T60	36
auto[0]	auto[0]	interest[1]	603	1			T17	18		T60	11		T61	1
auto[0]	auto[0]	interest[4]	3596	1			T15	1		T17	111		T18	1
auto[0]	auto[0]	interest[64]	1816	1			T17	54		T60	57		T61	4
auto[0]	auto[1]	others[0]	10322	1			T12	18		T13	38		T19	347
auto[0]	auto[1]	others[1]	1613	1			T13	9		T19	57		T23	28
auto[0]	auto[1]	others[2]	1578	1			T13	7		T19	47		T23	27
auto[0]	auto[1]	others[3]	1885	1			T13	12		T19	74		T23	44
auto[0]	auto[1]	interest[1]	1030	1			T13	4		T19	25		T23	15
auto[0]	auto[1]	interest[4]	6913	1			T12	18		T13	23		T19	216
auto[0]	auto[1]	interest[64]	3186	1			T13	9		T19	110		T23	54
auto[1]	auto[0]	others[0]	3284	1			T17	85		T18	3		T60	102
auto[1]	auto[0]	others[1]	553	1			T17	15		T60	15		T61	2
auto[1]	auto[0]	others[2]	562	1			T15	1		T17	13		T60	17
auto[1]	auto[0]	others[3]	571	1			T15	2		T17	20		T60	16
auto[1]	auto[0]	interest[1]	339	1			T17	14		T60	17		T62	7
auto[1]	auto[0]	interest[4]	2088	1			T17	52		T18	2		T60	62
auto[1]	auto[0]	interest[64]	1068	1			T15	1		T17	28		T60	35

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal