Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	500	1			T2	17		T42	20		T43	31
all_values[1]	500	1			T2	17		T42	20		T43	31
all_values[2]	500	1			T2	17		T42	20		T43	31
all_values[3]	500	1			T2	17		T42	20		T43	31
all_values[4]	500	1			T2	17		T42	20		T43	31
all_values[5]	500	1			T2	17		T42	20		T43	31
all_values[6]	500	1			T2	17		T42	20		T43	31
all_values[7]	500	1			T2	17		T42	20		T43	31

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2140

1

T2

74

T42

82

T43

137

auto[1]

1860

1

T2

62

T42

78

T43

111

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1602

1

T2

51

T42

56

T43

96

auto[1]

2398

1

T2

85

T42

104

T43

152

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2305

1

T2

72

T42

84

T43

136

auto[1]

1695

1

T2

64

T42

76

T43

112

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	103	1			T2	3		T42	5		T43	5
all_values[0]	auto[0]	auto[0]	auto[1]	46	1			T2	2		T42	2		T43	7
all_values[0]	auto[0]	auto[1]	auto[0]	74	1			T2	4		T42	2		T43	2
all_values[0]	auto[0]	auto[1]	auto[1]	52	1			T2	2		T42	2		T43	2
all_values[0]	auto[1]	auto[0]	auto[1]	117	1			T2	4		T42	6		T43	6
all_values[0]	auto[1]	auto[1]	auto[1]	108	1			T2	2		T42	3		T43	9
all_values[1]	auto[0]	auto[0]	auto[0]	107	1			T2	6		T42	3		T43	6
all_values[1]	auto[0]	auto[0]	auto[1]	53	1			T2	2		T42	3		T43	3
all_values[1]	auto[0]	auto[1]	auto[0]	76	1			T2	2		T42	2		T43	7
all_values[1]	auto[0]	auto[1]	auto[1]	53	1			T2	1		T42	2		T43	2
all_values[1]	auto[1]	auto[0]	auto[1]	120	1			T2	3		T42	3		T43	9
all_values[1]	auto[1]	auto[1]	auto[1]	91	1			T2	3		T42	7		T43	4
all_values[2]	auto[0]	auto[0]	auto[0]	122	1			T2	3		T42	4		T43	6
all_values[2]	auto[0]	auto[0]	auto[1]	36	1			T42	3		T43	1		T163	1
all_values[2]	auto[0]	auto[1]	auto[0]	88	1			T2	3		T42	2		T43	4
all_values[2]	auto[0]	auto[1]	auto[1]	44	1			T2	3		T42	1		T43	3
all_values[2]	auto[1]	auto[0]	auto[1]	123	1			T2	5		T42	4		T43	9
all_values[2]	auto[1]	auto[1]	auto[1]	87	1			T2	3		T42	6		T43	8
all_values[3]	auto[0]	auto[0]	auto[0]	104	1			T2	3		T42	1		T43	7
all_values[3]	auto[0]	auto[0]	auto[1]	62	1			T2	1		T42	5		T43	3
all_values[3]	auto[0]	auto[1]	auto[0]	93	1			T2	2		T42	3		T43	8
all_values[3]	auto[0]	auto[1]	auto[1]	38	1			T2	2		T42	3		T43	3
all_values[3]	auto[1]	auto[0]	auto[1]	110	1			T2	6		T42	4		T43	5
all_values[3]	auto[1]	auto[1]	auto[1]	93	1			T2	3		T42	4		T43	5
all_values[4]	auto[0]	auto[0]	auto[0]	103	1			T2	5		T42	3		T43	3
all_values[4]	auto[0]	auto[0]	auto[1]	40	1			T42	1		T43	2		T352	1
all_values[4]	auto[0]	auto[1]	auto[0]	87	1			T2	3		T42	5		T43	6
all_values[4]	auto[0]	auto[1]	auto[1]	48	1			T2	1		T43	3		T163	2
all_values[4]	auto[1]	auto[0]	auto[1]	122	1			T2	4		T42	3		T43	8
all_values[4]	auto[1]	auto[1]	auto[1]	100	1			T2	4		T42	8		T43	9
all_values[5]	auto[0]	auto[0]	auto[0]	153	1			T2	4		T42	5		T43	8
all_values[5]	auto[0]	auto[1]	auto[0]	155	1			T2	4		T42	6		T43	8
all_values[5]	auto[1]	auto[0]	auto[1]	111	1			T2	6		T42	3		T43	10
all_values[5]	auto[1]	auto[1]	auto[1]	81	1			T2	3		T42	6		T43	5
all_values[6]	auto[0]	auto[0]	auto[0]	89	1			T2	2		T42	6		T43	7
all_values[6]	auto[0]	auto[0]	auto[1]	58	1			T2	2		T42	2		T43	5
all_values[6]	auto[0]	auto[1]	auto[0]	65	1			T2	1		T42	5		T43	2
all_values[6]	auto[0]	auto[1]	auto[1]	63	1			T2	3		T43	4		T163	1
all_values[6]	auto[1]	auto[0]	auto[1]	118	1			T2	2		T42	4		T43	8
all_values[6]	auto[1]	auto[1]	auto[1]	107	1			T2	7		T42	3		T43	5
all_values[7]	auto[0]	auto[0]	auto[0]	99	1			T2	4		T42	4		T43	13
all_values[7]	auto[0]	auto[0]	auto[1]	53	1			T2	2		T42	2		T43	2
all_values[7]	auto[0]	auto[1]	auto[0]	84	1			T2	2		T43	4		T163	3
all_values[7]	auto[0]	auto[1]	auto[1]	57	1			T42	2		T163	7		T164	3
all_values[7]	auto[1]	auto[0]	auto[1]	91	1			T2	5		T42	6		T43	4
all_values[7]	auto[1]	auto[1]	auto[1]	116	1			T2	4		T42	6		T43	8

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal