Group : spi_device_env_pkg::spi_device_env_cov::all_modes_cg
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Group : spi_device_env_pkg::spi_device_env_cov::all_modes_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
63.64 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv


Summary for Group spi_device_env_pkg::spi_device_env_cov::all_modes_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 5 1 4 80.00
Crosses 6 3 3 50.00


Variables for Group spi_device_env_pkg::spi_device_env_cov::all_modes_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mode 3 1 2 66.67 100 1 1 0
cp_tpm_enabled 2 0 2 100.00 100 1 1 2


Crosses for Group spi_device_env_pkg::spi_device_env_cov::all_modes_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 6 3 3 50.00 100 1 1 0


Summary for Variable cp_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 3 1 2 66.67


Automatically Generated Bins for cp_mode

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
auto[DisabledMode] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[FlashMode] 37907 1 T5 23 T12 18 T13 79
auto[PassthroughMode] 4710 1 T1 38 T4 18 T6 4


Summary for Variable cp_tpm_enabled

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_tpm_enabled

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 5767 1 T1 38 T4 18 T5 23
auto[1] 36850 1 T12 18 T13 79 T19 660


Summary for Cross cr_all

Samples crossed: cp_mode cp_tpm_enabled
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 6 3 3 50.00 3


Automatically Generated Cross Bins for cr_all

Element holes
cp_modecp_tpm_enabledCOUNTAT LEASTNUMBERSTATUS
[auto[DisabledMode]] * -- -- 2


Uncovered bins
cp_modecp_tpm_enabledCOUNTAT LEASTNUMBERSTATUS
[auto[PassthroughMode]] [auto[1]] 0 1 1


Covered bins
cp_modecp_tpm_enabledCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[FlashMode] auto[0] 1057 1 T5 23 T10 23 T70 29
auto[FlashMode] auto[1] 36850 1 T12 18 T13 79 T19 660
auto[PassthroughMode] auto[0] 4710 1 T1 38 T4 18 T6 4

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