Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	332628	1			T1	1		T2	1		T3	1
all_values[1]	332628	1			T1	1		T2	1		T3	1
all_values[2]	332628	1			T1	1		T2	1		T3	1
all_values[3]	332628	1			T1	1		T2	1		T3	1
all_values[4]	332628	1			T1	1		T2	1		T3	1
all_values[5]	332628	1			T1	1		T2	1		T3	1
all_values[6]	332628	1			T1	1		T2	1		T3	1
all_values[7]	332628	1			T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2658726

1

T1

8

T2

8

T3

8

auto[1]

2298

1

T20

49

T30

74

T38

77

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2658832

1

T1

8

T2

8

T3

8

auto[1]

2192

1

T16

4

T20

46

T61

1

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	332233	1			T1	1		T2	1		T3	1
all_values[0]	auto[0]	auto[1]	141	1			T20	7		T30	1		T38	3
all_values[0]	auto[1]	auto[0]	144	1			T20	2		T30	5		T38	4
all_values[0]	auto[1]	auto[1]	110	1			T30	3		T38	1		T39	4
all_values[1]	auto[0]	auto[0]	332202	1			T1	1		T2	1		T3	1
all_values[1]	auto[0]	auto[1]	107	1			T20	3		T30	2		T38	5
all_values[1]	auto[1]	auto[0]	180	1			T20	3		T30	13		T38	7
all_values[1]	auto[1]	auto[1]	139	1			T20	4		T30	3		T38	2
all_values[2]	auto[0]	auto[0]	332222	1			T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	102	1			T20	1		T30	4		T38	3
all_values[2]	auto[1]	auto[0]	165	1			T20	2		T30	7		T38	7
all_values[2]	auto[1]	auto[1]	139	1			T20	8		T38	5		T39	1
all_values[3]	auto[0]	auto[0]	332190	1			T1	1		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	138	1			T30	2		T38	4		T39	5
all_values[3]	auto[1]	auto[0]	170	1			T20	2		T30	4		T38	6
all_values[3]	auto[1]	auto[1]	130	1			T20	1		T30	1		T38	2
all_values[4]	auto[0]	auto[0]	332206	1			T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	142	1			T20	2		T78	1		T38	1
all_values[4]	auto[1]	auto[0]	149	1			T20	7		T30	10		T38	7
all_values[4]	auto[1]	auto[1]	131	1			T20	1		T30	2		T38	4
all_values[5]	auto[0]	auto[0]	331986	1			T1	1		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	359	1			T16	4		T20	3		T61	1
all_values[5]	auto[1]	auto[0]	170	1			T20	3		T30	9		T38	2
all_values[5]	auto[1]	auto[1]	113	1			T20	5		T38	5		T39	2
all_values[6]	auto[0]	auto[0]	332228	1			T1	1		T2	1		T3	1
all_values[6]	auto[0]	auto[1]	125	1			T20	3		T30	3		T38	1
all_values[6]	auto[1]	auto[0]	172	1			T20	4		T30	6		T38	9
all_values[6]	auto[1]	auto[1]	103	1			T20	4		T30	5		T38	4
all_values[7]	auto[0]	auto[0]	332237	1			T1	1		T2	1		T3	1
all_values[7]	auto[0]	auto[1]	108	1			T20	3		T30	3		T38	1
all_values[7]	auto[1]	auto[0]	178	1			T20	2		T30	6		T38	7
all_values[7]	auto[1]	auto[1]	105	1			T20	1		T38	5		T39	2