Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
72.95	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	1	37	97.37
Crosses	84	32	52	61.90

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	1	1	50.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	28	20	41.67	100	1	1	0
cr_modeXdummyXnum_lanes	36	4	32	88.89	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	1218	1			T6	6		T9	6		T10	4
auto[SpiFlashAddrCfg]	787	1			T5	4		T6	10		T7	2
auto[SpiFlashAddr3b]	1100	1			T5	10		T6	8		T11	10
auto[SpiFlashAddr4b]	894	1			T5	20		T7	4		T9	14

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3043

1

T7

6

T9

24

T10

4

auto[1]

956

1

T5

34

T6

24

T65

30

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2085

1

T5

26

T6

10

T7

4

auto[1]

1914

1

T5

8

T6

14

T7

2

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1634	1			T5	22		T6	6		T9	12
values[1]	98	1			T236	4		T262	10		T182	8
values[2]	182	1			T9	4		T77	2		T25	4
values[3]	197	1			T6	2		T9	2		T11	2
values[4]	154	1			T85	7		T66	8		T299	5
values[5]	150	1			T9	2		T65	4		T41	2
values[6]	185	1			T5	2		T7	2		T13	2
values[7]	237	1			T65	6		T41	12		T42	2
values[8]	1162	1			T5	10		T6	16		T7	4

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3460

1

T5

34

T6

24

T7

6

auto[1]

539

1

T77

12

T85

10

T78

11

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

3907

1

T5

24

T6

24

T7

6

write

92

1

T5

10

T65

8

T53

4

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

1830

1

T5

14

T6

10

T7

4

valids[0x1]

2169

1

T5

20

T6

14

T7

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	196	1			T9	6		T11	4		T65	6
internal_process_ops[0x5a]	219	1			T41	8		T44	14		T56	4
internal_process_ops[0x05]	259	1			T6	2		T11	8		T41	8
internal_process_ops[0x35]	196	1			T65	2		T42	6		T45	6
internal_process_ops[0x15]	219	1			T41	2		T42	4		T45	4
internal_process_ops[0x03]	254	1			T5	2		T9	2		T13	2
internal_process_ops[0x0b]	296	1			T6	2		T9	2		T41	2
internal_process_ops[0x3b]	232	1			T5	2		T6	2		T11	2
internal_process_ops[0x6b]	244	1			T5	2		T11	10		T65	2
internal_process_ops[0xbb]	300	1			T11	2		T65	2		T77	3
internal_process_ops[0xeb]	325	1			T7	2		T11	6		T78	7

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3949

1

T5

24

T6

24

T7

6

auto[1]

50

1

T5

10

T65

8

T53

4

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_upload

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3999

1

T5

34

T6

24

T7

6

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	28	20	41.67	28
Automatically Generated Cross Bins	48	28	20	41.67	28
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Element holes

cp_is_flash	cp_is_write	cp_addr_mode	cp_addr_swap_en	cp_payload_swap_en	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[write]	*	[auto[0]]	[auto[1]]	--	--	4
[auto[0]]	[write]	*	[auto[1]]	[auto[0]]	--	--	4
[auto[1]]	[read]	*	[auto[1]]	[auto[0]]	--	--	4
[auto[1]]	[write]	*	*	*	--	--	16

Covered bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

926

1

T9

6

T10

4

T11

12

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

260

1

T6

6

T65

8

T53

10

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

433

1

T7

2

T9

4

T11

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

191

1

T5

4

T6

10

T65

6

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

616

1

T11

10

T13

2

T41

8

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

269

1

T5

10

T6

8

T65

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

487

1

T7

4

T9

14

T11

8

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

186

1

T5

10

T65

4

T181

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

14

1

T262

2

T187

4

T268

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

16

1

T65

6

T53

4

T66

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

4

1

T215

2

T300

2

-

-

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

10

1

T67

4

T73

2

T297

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

14

1

T206

2

T301

8

T212

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

12

1

T65

2

T68

2

T70

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

10

1

T277

4

T246

2

T302

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

12

1

T5

10

T284

2

-

-

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

2

1

T303

2

-

-

-

-

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

149

1

T77

12

T299

13

T80

6

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

189

1

T78

4

T79

16

T299

5

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

199

1

T85

10

T78

7

T80

2

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	4	32	88.89	4

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Uncovered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[1]]	[valids[0x0]]	0	1	1
[auto[1]]	[values[0] , values[1]]	[valids[0x0]]	--	--	2
[auto[1]]	[values[7]]	[valids[0x1]]	0	1	1

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	306	1			T5	6		T6	4		T10	4
auto[0]	values[0]	valids[0x1]	1250	1			T5	16		T6	2		T9	12
auto[0]	values[1]	valids[0x1]	89	1			T236	4		T262	10		T182	8
auto[0]	values[2]	valids[0x0]	70	1			T9	4		T25	2		T223	4
auto[0]	values[2]	valids[0x1]	48	1			T25	2		T67	4		T199	6
auto[0]	values[3]	valids[0x0]	116	1			T11	2		T65	2		T56	4
auto[0]	values[3]	valids[0x1]	50	1			T6	2		T9	2		T56	4
auto[0]	values[4]	valids[0x0]	79	1			T66	8		T199	2		T26	3
auto[0]	values[4]	valids[0x1]	35	1			T223	4		T26	1		T46	6
auto[0]	values[5]	valids[0x0]	88	1			T53	2		T66	10		T197	2
auto[0]	values[5]	valids[0x1]	42	1			T9	2		T65	4		T41	2
auto[0]	values[6]	valids[0x0]	104	1			T5	2		T83	2		T52	6
auto[0]	values[6]	valids[0x1]	44	1			T7	2		T13	2		T262	2
auto[0]	values[7]	valids[0x0]	141	1			T65	6		T41	4		T42	2
auto[0]	values[7]	valids[0x1]	58	1			T41	8		T56	2		T75	4
auto[0]	values[8]	valids[0x0]	581	1			T5	6		T6	6		T7	4
auto[0]	values[8]	valids[0x1]	359	1			T5	4		T6	10		T9	4
auto[1]	values[0]	valids[0x1]	78	1			T85	3		T79	3		T299	5
auto[1]	values[1]	valids[0x1]	9	1			T304	5		T303	2		T305	2
auto[1]	values[2]	valids[0x0]	53	1			T80	4		T306	7		T307	4
auto[1]	values[2]	valids[0x1]	11	1			T77	2		T308	9		-	-
auto[1]	values[3]	valids[0x0]	29	1			T78	11		T306	3		T309	4
auto[1]	values[3]	valids[0x1]	2	1			T307	2		-	-		-	-
auto[1]	values[4]	valids[0x0]	29	1			T299	5		T80	5		T114	2
auto[1]	values[4]	valids[0x1]	11	1			T85	7		T310	2		T311	2
auto[1]	values[5]	valids[0x0]	12	1			T114	4		T305	6		T312	2
auto[1]	values[5]	valids[0x1]	8	1			T306	4		T313	4		-	-
auto[1]	values[6]	valids[0x0]	27	1			T314	3		T304	4		T315	5
auto[1]	values[6]	valids[0x1]	10	1			T316	10		-	-		-	-
auto[1]	values[7]	valids[0x0]	38	1			T79	7		T317	4		T307	2
auto[1]	values[8]	valids[0x0]	157	1			T77	10		T299	8		T114	6
auto[1]	values[8]	valids[0x1]	65	1			T79	6		T80	8		T114	6