Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg
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Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
36.36 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv


Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 16 2 14 87.50
Crosses 72 54 18 25.00


Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_busy_bit 2 1 1 50.00 100 1 1 2
cp_is_host_read 2 0 2 100.00 100 1 1 2
cp_other_status 8 0 8 100.00 100 1 1 8
cp_sw_read_while_csb_active 2 0 2 100.00 100 1 1 2
cp_wel_bit 2 1 1 50.00 100 1 1 2


Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all_except_csb 64 48 16 25.00 100 1 1 0
cr_busyXwelXcsb 8 6 2 25.00 100 1 1 0


Summary for Variable cp_busy_bit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_busy_bit

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1781686 1 T8 3008 T5 1 T6 1


Summary for Variable cp_is_host_read

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_is_host_read

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1656827 1 T8 3008 T5 1 T6 1
auto[1] 124859 1 T41 2082 T42 2618 T43 1374


Summary for Variable cp_other_status

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 8 0 8 100.00


Automatically Generated Bins for cp_other_status

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:524287] 382715 1 T8 811 T5 1 T6 1
auto[524288:1048575] 209706 1 T8 200 T11 1513 T41 1813
auto[1048576:1572863] 230372 1 T8 205 T11 1724 T41 2170
auto[1572864:2097151] 205028 1 T8 1181 T10 2 T11 3318
auto[2097152:2621439] 178426 1 T10 32 T11 362 T41 1172
auto[2621440:3145727] 173582 1 T8 106 T11 2112 T41 687
auto[3145728:3670015] 177310 1 T8 405 T11 343 T13 1
auto[3670016:4194303] 224547 1 T8 100 T11 788 T13 1


Summary for Variable cp_sw_read_while_csb_active

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_sw_read_while_csb_active

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 138318 1 T8 83 T5 1 T6 1
auto[1] 1643368 1 T8 2925 T10 71 T11 10577


Summary for Variable cp_wel_bit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_wel_bit

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1781686 1 T8 3008 T5 1 T6 1


Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 48 16 25.00 48


Automatically Generated Cross Bins for cr_all_except_csb

Element holes
cp_busy_bitcp_wel_bitcp_other_statuscp_is_host_readCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[1]] * * -- -- 16
[auto[1]] * * * -- -- 32


Covered bins
cp_busy_bitcp_wel_bitcp_other_statuscp_is_host_readCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0:524287] auto[0] 285831 1 T8 811 T5 1 T6 1
auto[0] auto[0] auto[0:524287] auto[1] 96884 1 T41 1042 T42 1581 T43 327
auto[0] auto[0] auto[524288:1048575] auto[0] 204572 1 T8 200 T11 1513 T41 1556
auto[0] auto[0] auto[524288:1048575] auto[1] 5134 1 T41 257 T42 3 T176 180
auto[0] auto[0] auto[1048576:1572863] auto[0] 226619 1 T8 205 T11 1724 T41 2159
auto[0] auto[0] auto[1048576:1572863] auto[1] 3753 1 T41 11 T42 138 T176 1
auto[0] auto[0] auto[1572864:2097151] auto[0] 200330 1 T8 1181 T10 2 T11 3318
auto[0] auto[0] auto[1572864:2097151] auto[1] 4698 1 T41 769 T42 127 T43 512
auto[0] auto[0] auto[2097152:2621439] auto[0] 176662 1 T10 32 T11 362 T41 1172
auto[0] auto[0] auto[2097152:2621439] auto[1] 1764 1 T42 255 T43 18 T46 1
auto[0] auto[0] auto[2621440:3145727] auto[0] 170440 1 T8 106 T11 2112 T41 687
auto[0] auto[0] auto[2621440:3145727] auto[1] 3142 1 T42 257 T43 12 T176 77
auto[0] auto[0] auto[3145728:3670015] auto[0] 176639 1 T8 405 T11 343 T13 1
auto[0] auto[0] auto[3145728:3670015] auto[1] 671 1 T42 2 T177 3 T178 1
auto[0] auto[0] auto[3670016:4194303] auto[0] 215734 1 T8 100 T11 788 T13 1
auto[0] auto[0] auto[3670016:4194303] auto[1] 8813 1 T41 3 T42 255 T43 505


Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 6 2 25.00 6


Automatically Generated Cross Bins for cr_busyXwelXcsb

Element holes
cp_busy_bitcp_wel_bitcp_sw_read_while_csb_activeCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[1]] * -- -- 2
[auto[1]] * * -- -- 4


Covered bins
cp_busy_bitcp_wel_bitcp_sw_read_while_csb_activeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] 138318 1 T8 83 T5 1 T6 1
auto[0] auto[0] auto[1] 1643368 1 T8 2925 T10 71 T11 10577

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