Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	29	99	77.34

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	29	99	77.34	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2504

1

T7

6

T9

24

T10

4

auto[1]

956

1

T5

34

T6

24

T65

30

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	418	1			T180	2		T56	20		T24	18
values[1]	580	1			T6	24		T11	32		T41	24
values[2]	442	1			T181	2		T45	24		T179	6
values[3]	394	1			T13	2		T44	22		T262	38
values[4]	400	1			T65	30		T43	10		T236	24
values[5]	400	1			T7	6		T9	24		T10	4
values[6]	534	1			T110	2		T83	4		T42	14
values[7]	292	1			T5	34		T128	2		T67	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	602	1			T9	24		T11	32		T13	2
values[1]	298	1			T5	34		T10	4		T180	2
values[2]	458	1			T110	2		T83	4		T128	2
values[3]	434	1			T44	22		T23	12		T43	10
values[4]	392	1			T242	14		T236	24		T262	38
values[5]	408	1			T7	6		T68	24		T223	24
values[6]	388	1			T6	24		T45	24		T53	36
values[7]	480	1			T65	30		T181	2		T52	8

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	29	99	77.34	29

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[2]]	[values[4]]	0	1	1
[auto[0]]	[values[4]]	[values[1]]	0	1	1
[auto[0]]	[values[7]]	[values[7]]	0	1	1
[auto[1]]	[values[0]]	[values[1]]	0	1	1
[auto[1]]	[values[0]]	[values[5]]	0	1	1
[auto[1]]	[values[0]]	[values[7]]	0	1	1
[auto[1]]	[values[1]]	[values[2]]	0	1	1
[auto[1]]	[values[1]]	[values[5]]	0	1	1
[auto[1]]	[values[2]]	[values[0] , values[1]]	--	--	2
[auto[1]]	[values[2]]	[values[3] , values[4]]	--	--	2
[auto[1]]	[values[2]]	[values[6]]	0	1	1
[auto[1]]	[values[3]]	[values[3]]	0	1	1
[auto[1]]	[values[3]]	[values[6]]	0	1	1
[auto[1]]	[values[4]]	[values[3]]	0	1	1
[auto[1]]	[values[4]]	[values[5] , values[6]]	--	--	2
[auto[1]]	[values[5]]	[values[0]]	0	1	1
[auto[1]]	[values[5]]	[values[4] , values[5]]	--	--	2
[auto[1]]	[values[6]]	[values[2] , values[3]]	--	--	2
[auto[1]]	[values[6]]	[values[5] , values[6] , values[7]]	--	--	3
[auto[1]]	[values[7]]	[values[4] , values[5] , values[6]]	--	--	3

Covered bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	42	1			T244	6		T280	4		T259	24
auto[0]	values[0]	values[1]	58	1			T180	2		T82	10		T226	28
auto[0]	values[0]	values[2]	40	1			T56	20		T228	8		T318	12
auto[0]	values[0]	values[3]	10	1			T294	10		-	-		-	-
auto[0]	values[0]	values[4]	14	1			T84	14		-	-		-	-
auto[0]	values[0]	values[5]	82	1			T268	30		T200	14		T112	24
auto[0]	values[0]	values[6]	26	1			T24	18		T27	4		T276	4
auto[0]	values[0]	values[7]	22	1			T74	22		-	-		-	-
auto[0]	values[1]	values[0]	138	1			T11	32		T41	24		T234	14
auto[0]	values[1]	values[1]	32	1			T290	14		T237	4		T319	14
auto[0]	values[1]	values[2]	78	1			T224	2		T320	14		T209	18
auto[0]	values[1]	values[3]	42	1			T277	16		T321	26		-	-
auto[0]	values[1]	values[4]	56	1			T206	8		T205	14		T302	28
auto[0]	values[1]	values[5]	18	1			T265	18		-	-		-	-
auto[0]	values[1]	values[6]	14	1			T322	14		-	-		-	-
auto[0]	values[1]	values[7]	46	1			T176	12		T261	4		T323	22
auto[0]	values[2]	values[0]	22	1			T278	8		T324	14		-	-
auto[0]	values[2]	values[1]	34	1			T177	12		T204	6		T107	16
auto[0]	values[2]	values[2]	8	1			T282	4		T210	4		-	-
auto[0]	values[2]	values[3]	54	1			T272	22		T221	18		T218	14
auto[0]	values[2]	values[5]	88	1			T325	28		T326	28		T285	10
auto[0]	values[2]	values[6]	52	1			T45	24		T327	28		-	-
auto[0]	values[2]	values[7]	110	1			T250	14		T75	28		T291	8
auto[0]	values[3]	values[0]	14	1			T13	2		T283	12		-	-
auto[0]	values[3]	values[1]	34	1			T191	22		T279	12		-	-
auto[0]	values[3]	values[2]	4	1			T328	4		-	-		-	-
auto[0]	values[3]	values[3]	50	1			T44	22		T329	28		-	-
auto[0]	values[3]	values[4]	52	1			T262	38		T178	14		-	-
auto[0]	values[3]	values[5]	68	1			T223	24		T192	16		T225	28
auto[0]	values[3]	values[6]	38	1			T184	18		T330	14		T331	6
auto[0]	values[3]	values[7]	20	1			T188	12		T213	8		-	-
auto[0]	values[4]	values[0]	20	1			T26	12		T252	8		-	-
auto[0]	values[4]	values[2]	74	1			T194	8		T332	24		T249	20
auto[0]	values[4]	values[3]	26	1			T43	10		T197	16		-	-
auto[0]	values[4]	values[4]	56	1			T236	24		T76	24		T195	8
auto[0]	values[4]	values[5]	10	1			T333	2		T334	8		-	-
auto[0]	values[4]	values[6]	56	1			T182	18		T97	8		T246	24
auto[0]	values[4]	values[7]	26	1			T105	4		T201	8		T300	4
auto[0]	values[5]	values[0]	58	1			T9	24		T111	10		T335	24
auto[0]	values[5]	values[1]	4	1			T10	4		-	-		-	-
auto[0]	values[5]	values[2]	50	1			T187	12		T227	6		T251	4
auto[0]	values[5]	values[3]	62	1			T231	26		T245	26		T336	10
auto[0]	values[5]	values[4]	26	1			T337	26		-	-		-	-
auto[0]	values[5]	values[5]	26	1			T7	6		T99	20		-	-
auto[0]	values[5]	values[6]	12	1			T287	2		T113	10		-	-
auto[0]	values[5]	values[7]	8	1			T52	8		-	-		-	-
auto[0]	values[6]	values[0]	128	1			T42	14		T260	6		T220	36
auto[0]	values[6]	values[1]	16	1			T338	4		T339	12		-	-
auto[0]	values[6]	values[2]	48	1			T110	2		T83	4		T258	18
auto[0]	values[6]	values[3]	78	1			T23	12		T25	12		T233	14
auto[0]	values[6]	values[4]	14	1			T242	14		-	-		-	-
auto[0]	values[6]	values[5]	26	1			T247	10		T239	14		T340	2
auto[0]	values[6]	values[6]	22	1			T131	10		T199	12		-	-
auto[0]	values[6]	values[7]	86	1			T106	8		T341	8		T216	16
auto[0]	values[7]	values[0]	60	1			T275	16		T98	6		T301	30
auto[0]	values[7]	values[1]	8	1			T104	8		-	-		-	-
auto[0]	values[7]	values[2]	10	1			T128	2		T342	6		T343	2
auto[0]	values[7]	values[3]	34	1			T254	6		T257	10		T229	18
auto[0]	values[7]	values[4]	22	1			T271	8		T295	8		T344	6
auto[0]	values[7]	values[5]	44	1			T269	10		T286	34		-	-
auto[0]	values[7]	values[6]	28	1			T183	10		T219	2		T214	6
auto[1]	values[0]	values[0]	32	1			T345	32		-	-		-	-
auto[1]	values[0]	values[2]	10	1			T256	10		-	-		-	-
auto[1]	values[0]	values[3]	42	1			T232	20		T346	22		-	-
auto[1]	values[0]	values[4]	10	1			T70	10		-	-		-	-
auto[1]	values[0]	values[6]	30	1			T73	30		-	-		-	-
auto[1]	values[1]	values[0]	20	1			T347	20		-	-		-	-
auto[1]	values[1]	values[1]	6	1			T185	6		-	-		-	-
auto[1]	values[1]	values[3]	18	1			T207	18		-	-		-	-
auto[1]	values[1]	values[4]	26	1			T348	26		-	-		-	-
auto[1]	values[1]	values[6]	52	1			T6	24		T289	28		-	-
auto[1]	values[1]	values[7]	34	1			T230	34		-	-		-	-
auto[1]	values[2]	values[2]	6	1			T179	6		-	-		-	-
auto[1]	values[2]	values[5]	40	1			T68	24		T198	2		T71	14
auto[1]	values[2]	values[7]	28	1			T181	2		T240	26		-	-
auto[1]	values[3]	values[0]	10	1			T274	10		-	-		-	-
auto[1]	values[3]	values[1]	14	1			T284	14		-	-		-	-
auto[1]	values[3]	values[2]	30	1			T349	30		-	-		-	-
auto[1]	values[3]	values[4]	20	1			T293	20		-	-		-	-
auto[1]	values[3]	values[5]	6	1			T255	6		-	-		-	-
auto[1]	values[3]	values[7]	34	1			T238	16		T350	8		T253	10
auto[1]	values[4]	values[0]	8	1			T26	8		-	-		-	-
auto[1]	values[4]	values[1]	28	1			T69	28		-	-		-	-
auto[1]	values[4]	values[2]	44	1			T351	32		T281	12		-	-
auto[1]	values[4]	values[4]	22	1			T235	20		T352	2		-	-
auto[1]	values[4]	values[7]	30	1			T65	30		-	-		-	-
auto[1]	values[5]	values[1]	20	1			T353	20		-	-		-	-
auto[1]	values[5]	values[2]	36	1			T66	36		-	-		-	-
auto[1]	values[5]	values[3]	12	1			T241	12		-	-		-	-
auto[1]	values[5]	values[6]	58	1			T53	36		T54	22		-	-
auto[1]	values[5]	values[7]	28	1			T248	28		-	-		-	-
auto[1]	values[6]	values[0]	32	1			T297	32		-	-		-	-
auto[1]	values[6]	values[1]	10	1			T170	10		-	-		-	-
auto[1]	values[6]	values[4]	74	1			T196	22		T354	4		T203	18
auto[1]	values[7]	values[0]	18	1			T298	18		-	-		-	-
auto[1]	values[7]	values[1]	34	1			T5	34		-	-		-	-
auto[1]	values[7]	values[2]	20	1			T67	20		-	-		-	-
auto[1]	values[7]	values[3]	6	1			T72	6		-	-		-	-
auto[1]	values[7]	values[7]	8	1			T211	8		-	-		-	-