Group : spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg
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Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 66 0 66 100.00
Crosses 128 0 128 100.00


Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_filtered 2 0 2 100.00 100 1 1 2
cp_opcode 64 0 64 100.00 100 1 1 64


Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 128 0 128 100.00 100 1 1 0


Summary for Variable cp_filtered

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_filtered

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1731 1 T5 17 T6 12 T7 3
auto[1] 2268 1 T5 17 T6 12 T7 3



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 64 0 64 100.00


Automatically Generated Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:3] 264 1 T5 2 T6 2 T9 2
auto[4:7] 307 1 T6 2 T10 4 T11 8
auto[8:11] 311 1 T5 4 T6 2 T9 2
auto[12:15] 14 1 T200 2 T231 2 T259 2
auto[16:19] 24 1 T65 4 T248 6 T76 6
auto[20:23] 239 1 T5 2 T41 2 T42 4
auto[24:27] 16 1 T9 4 T207 2 T255 2
auto[28:31] 12 1 T293 2 T183 2 T196 4
auto[32:35] 18 1 T262 10 T230 2 T211 2
auto[36:39] 12 1 T293 2 T246 2 T321 4
auto[40:43] 6 1 T170 2 T231 2 T291 2
auto[44:47] 14 1 T5 2 T223 2 T378 2
auto[48:51] 8 1 T9 2 T74 2 T296 2
auto[52:55] 210 1 T65 2 T42 6 T45 6
auto[56:59] 244 1 T5 2 T6 6 T11 2
auto[60:63] 36 1 T6 4 T66 10 T234 6
auto[64:67] 12 1 T293 4 T207 4 T379 2
auto[68:71] 18 1 T197 2 T68 2 T256 4
auto[72:75] 22 1 T66 2 T236 4 T74 2
auto[76:79] 26 1 T25 4 T230 8 T207 4
auto[80:83] 26 1 T66 2 T236 2 T197 2
auto[84:87] 26 1 T5 6 T7 2 T75 4
auto[88:91] 239 1 T41 8 T44 14 T56 4
auto[92:95] 20 1 T7 2 T9 6 T241 2
auto[96:99] 12 1 T187 2 T204 2 T227 2
auto[100:103] 8 1 T263 4 T267 2 T359 2
auto[104:107] 253 1 T5 2 T11 10 T65 2
auto[108:111] 26 1 T65 6 T68 4 T268 2
auto[112:115] 12 1 T53 2 T216 2 T329 2
auto[116:119] 12 1 T67 4 T197 4 T329 4
auto[120:123] 18 1 T233 2 T332 2 T245 2
auto[124:127] 14 1 T233 4 T351 4 T277 2
auto[128:131] 18 1 T56 4 T74 4 T273 4
auto[132:135] 6 1 T56 2 T268 4 - -
auto[136:139] 14 1 T183 2 T268 2 T248 2
auto[140:143] 8 1 T67 2 T231 2 T290 4
auto[144:147] 32 1 T6 4 T277 2 T254 2
auto[148:151] 14 1 T206 2 T332 2 T229 4
auto[152:155] 32 1 T6 4 T53 6 T74 2
auto[156:159] 214 1 T9 6 T11 4 T65 6
auto[160:163] 26 1 T187 4 T238 4 T269 2
auto[164:167] 22 1 T262 6 T185 2 T70 2
auto[168:171] 10 1 T181 2 T66 2 T72 2
auto[172:175] 24 1 T351 4 T75 2 T246 2
auto[176:179] 10 1 T54 4 T25 2 T323 4
auto[180:183] 69 1 T25 2 T24 6 T26 1
auto[184:187] 308 1 T9 2 T11 2 T65 2
auto[188:191] 12 1 T53 2 T232 2 T221 2
auto[192:195] 6 1 T70 2 T330 2 T190 2
auto[196:199] 4 1 T65 2 T268 2 - -
auto[200:203] 20 1 T67 6 T273 2 T217 2
auto[204:207] 18 1 T76 2 T321 2 T295 2
auto[208:211] 32 1 T5 8 T230 6 T245 2
auto[212:215] 22 1 T262 6 T273 2 T326 4
auto[216:219] 14 1 T53 4 T54 2 T199 4
auto[220:223] 30 1 T351 8 T223 2 T271 2
auto[224:227] 24 1 T65 6 T262 2 T293 2
auto[228:231] 24 1 T5 2 T53 2 T26 2
auto[232:235] 424 1 T7 2 T11 6 T78 7
auto[236:239] 16 1 T185 2 T69 2 T330 2
auto[240:243] 10 1 T200 2 T202 2 T215 4
auto[244:247] 13 1 T25 2 T250 2 T26 3
auto[248:251] 38 1 T5 4 T56 2 T187 4
auto[252:255] 6 1 T66 2 T298 4 - -



Summary for Cross cr_all

Samples crossed: cp_opcode cp_filtered
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 128 0 128 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_opcodecp_filteredCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:3] auto[0] 92 1 T5 1 T6 1 T9 1
auto[0:3] auto[1] 172 1 T5 1 T6 1 T9 1
auto[4:7] auto[0] 154 1 T6 1 T10 2 T11 4
auto[4:7] auto[1] 153 1 T6 1 T10 2 T11 4
auto[8:11] auto[0] 101 1 T5 2 T6 1 T9 1
auto[8:11] auto[1] 210 1 T5 2 T6 1 T9 1
auto[12:15] auto[0] 7 1 T200 1 T231 1 T259 1
auto[12:15] auto[1] 7 1 T200 1 T231 1 T259 1
auto[16:19] auto[0] 12 1 T65 2 T248 3 T76 3
auto[16:19] auto[1] 12 1 T65 2 T248 3 T76 3
auto[20:23] auto[0] 120 1 T5 1 T41 1 T42 2
auto[20:23] auto[1] 119 1 T5 1 T41 1 T42 2
auto[24:27] auto[0] 8 1 T9 2 T207 1 T255 1
auto[24:27] auto[1] 8 1 T9 2 T207 1 T255 1
auto[28:31] auto[0] 6 1 T293 1 T183 1 T196 2
auto[28:31] auto[1] 6 1 T293 1 T183 1 T196 2
auto[32:35] auto[0] 9 1 T262 5 T230 1 T211 1
auto[32:35] auto[1] 9 1 T262 5 T230 1 T211 1
auto[36:39] auto[0] 6 1 T293 1 T246 1 T321 2
auto[36:39] auto[1] 6 1 T293 1 T246 1 T321 2
auto[40:43] auto[0] 3 1 T170 1 T231 1 T291 1
auto[40:43] auto[1] 3 1 T170 1 T231 1 T291 1
auto[44:47] auto[0] 7 1 T5 1 T223 1 T378 1
auto[44:47] auto[1] 7 1 T5 1 T223 1 T378 1
auto[48:51] auto[0] 4 1 T9 1 T74 1 T296 1
auto[48:51] auto[1] 4 1 T9 1 T74 1 T296 1
auto[52:55] auto[0] 106 1 T65 1 T42 3 T45 3
auto[52:55] auto[1] 104 1 T65 1 T42 3 T45 3
auto[56:59] auto[0] 84 1 T5 1 T6 3 T11 1
auto[56:59] auto[1] 160 1 T5 1 T6 3 T11 1
auto[60:63] auto[0] 18 1 T6 2 T66 5 T234 3
auto[60:63] auto[1] 18 1 T6 2 T66 5 T234 3
auto[64:67] auto[0] 6 1 T293 2 T207 2 T379 1
auto[64:67] auto[1] 6 1 T293 2 T207 2 T379 1
auto[68:71] auto[0] 9 1 T197 1 T68 1 T256 2
auto[68:71] auto[1] 9 1 T197 1 T68 1 T256 2
auto[72:75] auto[0] 11 1 T66 1 T236 2 T74 1
auto[72:75] auto[1] 11 1 T66 1 T236 2 T74 1
auto[76:79] auto[0] 13 1 T25 2 T230 4 T207 2
auto[76:79] auto[1] 13 1 T25 2 T230 4 T207 2
auto[80:83] auto[0] 13 1 T66 1 T236 1 T197 1
auto[80:83] auto[1] 13 1 T66 1 T236 1 T197 1
auto[84:87] auto[0] 13 1 T5 3 T7 1 T75 2
auto[84:87] auto[1] 13 1 T5 3 T7 1 T75 2
auto[88:91] auto[0] 120 1 T41 4 T44 7 T56 2
auto[88:91] auto[1] 119 1 T41 4 T44 7 T56 2
auto[92:95] auto[0] 10 1 T7 1 T9 3 T241 1
auto[92:95] auto[1] 10 1 T7 1 T9 3 T241 1
auto[96:99] auto[0] 6 1 T187 1 T204 1 T227 1
auto[96:99] auto[1] 6 1 T187 1 T204 1 T227 1
auto[100:103] auto[0] 4 1 T263 2 T267 1 T359 1
auto[100:103] auto[1] 4 1 T263 2 T267 1 T359 1
auto[104:107] auto[0] 83 1 T5 1 T11 5 T65 1
auto[104:107] auto[1] 170 1 T5 1 T11 5 T65 1
auto[108:111] auto[0] 13 1 T65 3 T68 2 T268 1
auto[108:111] auto[1] 13 1 T65 3 T68 2 T268 1
auto[112:115] auto[0] 6 1 T53 1 T216 1 T329 1
auto[112:115] auto[1] 6 1 T53 1 T216 1 T329 1
auto[116:119] auto[0] 6 1 T67 2 T197 2 T329 2
auto[116:119] auto[1] 6 1 T67 2 T197 2 T329 2
auto[120:123] auto[0] 9 1 T233 1 T332 1 T245 1
auto[120:123] auto[1] 9 1 T233 1 T332 1 T245 1
auto[124:127] auto[0] 7 1 T233 2 T351 2 T277 1
auto[124:127] auto[1] 7 1 T233 2 T351 2 T277 1
auto[128:131] auto[0] 9 1 T56 2 T74 2 T273 2
auto[128:131] auto[1] 9 1 T56 2 T74 2 T273 2
auto[132:135] auto[0] 3 1 T56 1 T268 2 - -
auto[132:135] auto[1] 3 1 T56 1 T268 2 - -
auto[136:139] auto[0] 7 1 T183 1 T268 1 T248 1
auto[136:139] auto[1] 7 1 T183 1 T268 1 T248 1
auto[140:143] auto[0] 4 1 T67 1 T231 1 T290 2
auto[140:143] auto[1] 4 1 T67 1 T231 1 T290 2
auto[144:147] auto[0] 16 1 T6 2 T277 1 T254 1
auto[144:147] auto[1] 16 1 T6 2 T277 1 T254 1
auto[148:151] auto[0] 7 1 T206 1 T332 1 T229 2
auto[148:151] auto[1] 7 1 T206 1 T332 1 T229 2
auto[152:155] auto[0] 16 1 T6 2 T53 3 T74 1
auto[152:155] auto[1] 16 1 T6 2 T53 3 T74 1
auto[156:159] auto[0] 107 1 T9 3 T11 2 T65 3
auto[156:159] auto[1] 107 1 T9 3 T11 2 T65 3
auto[160:163] auto[0] 13 1 T187 2 T238 2 T269 1
auto[160:163] auto[1] 13 1 T187 2 T238 2 T269 1
auto[164:167] auto[0] 11 1 T262 3 T185 1 T70 1
auto[164:167] auto[1] 11 1 T262 3 T185 1 T70 1
auto[168:171] auto[0] 5 1 T181 1 T66 1 T72 1
auto[168:171] auto[1] 5 1 T181 1 T66 1 T72 1
auto[172:175] auto[0] 12 1 T351 2 T75 1 T246 1
auto[172:175] auto[1] 12 1 T351 2 T75 1 T246 1
auto[176:179] auto[0] 5 1 T54 2 T25 1 T323 2
auto[176:179] auto[1] 5 1 T54 2 T25 1 T323 2
auto[180:183] auto[0] 35 1 T25 1 T24 3 T26 1
auto[180:183] auto[1] 34 1 T25 1 T24 3 T247 5
auto[184:187] auto[0] 111 1 T9 1 T11 1 T65 1
auto[184:187] auto[1] 197 1 T9 1 T11 1 T65 1
auto[188:191] auto[0] 6 1 T53 1 T232 1 T221 1
auto[188:191] auto[1] 6 1 T53 1 T232 1 T221 1
auto[192:195] auto[0] 3 1 T70 1 T330 1 T190 1
auto[192:195] auto[1] 3 1 T70 1 T330 1 T190 1
auto[196:199] auto[0] 2 1 T65 1 T268 1 - -
auto[196:199] auto[1] 2 1 T65 1 T268 1 - -
auto[200:203] auto[0] 10 1 T67 3 T273 1 T217 1
auto[200:203] auto[1] 10 1 T67 3 T273 1 T217 1
auto[204:207] auto[0] 9 1 T76 1 T321 1 T295 1
auto[204:207] auto[1] 9 1 T76 1 T321 1 T295 1
auto[208:211] auto[0] 16 1 T5 4 T230 3 T245 1
auto[208:211] auto[1] 16 1 T5 4 T230 3 T245 1
auto[212:215] auto[0] 11 1 T262 3 T273 1 T326 2
auto[212:215] auto[1] 11 1 T262 3 T273 1 T326 2
auto[216:219] auto[0] 7 1 T53 2 T54 1 T199 2
auto[216:219] auto[1] 7 1 T53 2 T54 1 T199 2
auto[220:223] auto[0] 15 1 T351 4 T223 1 T271 1
auto[220:223] auto[1] 15 1 T351 4 T223 1 T271 1
auto[224:227] auto[0] 12 1 T65 3 T262 1 T293 1
auto[224:227] auto[1] 12 1 T65 3 T262 1 T293 1
auto[228:231] auto[0] 11 1 T5 1 T53 1 T251 1
auto[228:231] auto[1] 13 1 T5 1 T53 1 T26 2
auto[232:235] auto[0] 162 1 T7 1 T11 3 T23 4
auto[232:235] auto[1] 262 1 T7 1 T11 3 T78 7
auto[236:239] auto[0] 8 1 T185 1 T69 1 T330 1
auto[236:239] auto[1] 8 1 T185 1 T69 1 T330 1
auto[240:243] auto[0] 5 1 T200 1 T202 1 T215 2
auto[240:243] auto[1] 5 1 T200 1 T202 1 T215 2
auto[244:247] auto[0] 5 1 T25 1 T250 1 T75 1
auto[244:247] auto[1] 8 1 T25 1 T250 1 T26 3
auto[248:251] auto[0] 19 1 T5 2 T56 1 T187 2
auto[248:251] auto[1] 19 1 T5 2 T56 1 T187 2
auto[252:255] auto[0] 3 1 T66 1 T298 2 - -
auto[252:255] auto[1] 3 1 T66 1 T298 2 - -

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