Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.26	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	2	58	96.67

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	2	58	96.67	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	102	1			T11	20		T42	2		T242	2
auto[ReadAddrCrossIntoMailbox]	22	1			T272	4		T275	2		T184	4
auto[ReadAddrCrossOutOfMailbox]	31	1			T52	2		T272	4		T26	1
auto[ReadAddrCrossAllMailbox]	48	1			T13	2		T52	2		T242	4
auto[ReadAddrOutsideMailbox]	873	1			T5	6		T6	4		T7	2

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

540

1

T5

3

T6

2

T7

1

auto[1]

536

1

T5

3

T6

2

T7

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	175	1			T5	2		T9	2		T13	2
read_ops[0x0b]	186	1			T6	2		T9	2		T41	2
read_ops[0x3b]	154	1			T5	2		T6	2		T11	2
read_ops[0x6b]	155	1			T5	2		T11	10		T65	2
read_ops[0xbb]	201	1			T11	2		T65	2		T42	2
read_ops[0xeb]	205	1			T7	2		T11	6		T54	6

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	2	58	96.67	2

Automatically Generated Cross Bins for cr_all

Element holes

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	NUMBER	STATUS
[read_ops[0x0b]]	[auto[ReadAddrCrossOutOfMailbox]]	*	--	--	2

Covered bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	6	1			T272	1		T188	2		T258	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	6	1			T272	1		T188	2		T258	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	3	1			T272	2		T111	1		-	-
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	3	1			T272	2		T111	1		-	-
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	1	1			T272	1		-	-		-	-
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	1	1			T272	1		-	-		-	-
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	7	1			T13	1		T272	1		T111	2
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	7	1			T13	1		T272	1		T111	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	71	1			T5	1		T9	1		T179	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	70	1			T5	1		T9	1		T179	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	10	1			T242	1		T176	1		T178	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	10	1			T242	1		T176	1		T178	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	1	1			T257	1		-	-		-	-
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	1	1			T257	1		-	-		-	-
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	4	1			T242	2		T257	1		T258	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	4	1			T242	2		T257	1		T258	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	78	1			T6	1		T9	1		T41	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	78	1			T6	1		T9	1		T41	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	7	1			T11	1		T176	1		T184	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	7	1			T11	1		T176	1		T184	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	1	1			T220	1		-	-		-	-
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	1	1			T220	1		-	-		-	-
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	3	1			T220	2		T357	1		-	-
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	3	1			T220	2		T357	1		-	-
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	4	1			T184	1		T257	1		T278	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	4	1			T184	1		T257	1		T278	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	62	1			T5	1		T6	1		T41	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	62	1			T5	1		T6	1		T41	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	6	1			T11	5		T111	1		-	-
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	6	1			T11	5		T111	1		-	-
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	2	1			T258	2		-	-		-	-
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	2	1			T258	2		-	-		-	-
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	1	1			T52	1		-	-		-	-
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	1	1			T52	1		-	-		-	-
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	4	1			T52	1		T111	1		T258	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	4	1			T52	1		T111	1		T258	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	65	1			T5	1		T65	1		T83	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	64	1			T5	1		T65	1		T83	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	8	1			T11	1		T42	1		T184	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	8	1			T11	1		T42	1		T184	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	2	1			T275	1		T220	1		-	-
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	2	1			T275	1		T220	1		-	-
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	5	1			T26	1		T275	4		-	-
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	4	1			T275	4		-	-		-	-
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	3	1			T272	1		T220	2		-	-
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	3	1			T272	1		T220	2		-	-
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	83	1			T65	1		T53	2		T67	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	83	1			T65	1		T53	2		T67	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	14	1			T11	3		T272	1		T184	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	14	1			T11	3		T272	1		T184	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	2	1			T184	2		-	-		-	-
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	2	1			T184	2		-	-		-	-
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	6	1			T272	1		T184	1		T279	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	6	1			T272	1		T184	1		T279	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	2	1			T272	1		T218	1		-	-
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	2	1			T272	1		T218	1		-	-
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	79	1			T7	1		T54	3		T242	3
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	78	1			T7	1		T54	3		T242	3