Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	332628	1			T1	1		T2	1		T3	1
all_pins[1]	332628	1			T1	1		T2	1		T3	1
all_pins[2]	332628	1			T1	1		T2	1		T3	1
all_pins[3]	332628	1			T1	1		T2	1		T3	1
all_pins[4]	332628	1			T1	1		T2	1		T3	1
all_pins[5]	332628	1			T1	1		T2	1		T3	1
all_pins[6]	332628	1			T1	1		T2	1		T3	1
all_pins[7]	332628	1			T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2660054	1			T1	8		T2	8		T3	8
values[0x1]	970	1			T20	24		T30	14		T38	28
transitions[0x0=>0x1]	687	1			T20	16		T30	10		T38	21
transitions[0x1=>0x0]	701	1			T20	16		T30	10		T38	21

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	332518	1			T1	1		T2	1		T3	1
all_pins[0]	values[0x1]	110	1			T30	3		T38	1		T39	4
all_pins[0]	transitions[0x0=>0x1]	77	1			T39	2		T356	2		T162	1
all_pins[0]	transitions[0x1=>0x0]	106	1			T20	4		T38	1		T39	3
all_pins[1]	values[0x0]	332489	1			T1	1		T2	1		T3	1
all_pins[1]	values[0x1]	139	1			T20	4		T30	3		T38	2
all_pins[1]	transitions[0x0=>0x1]	92	1			T30	3		T38	1		T39	5
all_pins[1]	transitions[0x1=>0x0]	92	1			T20	4		T38	4		T39	1
all_pins[2]	values[0x0]	332489	1			T1	1		T2	1		T3	1
all_pins[2]	values[0x1]	139	1			T20	8		T38	5		T39	1
all_pins[2]	transitions[0x0=>0x1]	99	1			T20	7		T38	4		T39	1
all_pins[2]	transitions[0x1=>0x0]	90	1			T30	1		T38	1		T39	5
all_pins[3]	values[0x0]	332498	1			T1	1		T2	1		T3	1
all_pins[3]	values[0x1]	130	1			T20	1		T30	1		T38	2
all_pins[3]	transitions[0x0=>0x1]	93	1			T20	1		T38	2		T39	4
all_pins[3]	transitions[0x1=>0x0]	94	1			T20	1		T30	1		T38	4
all_pins[4]	values[0x0]	332497	1			T1	1		T2	1		T3	1
all_pins[4]	values[0x1]	131	1			T20	1		T30	2		T38	4
all_pins[4]	transitions[0x0=>0x1]	97	1			T20	1		T30	2		T38	4
all_pins[4]	transitions[0x1=>0x0]	79	1			T20	5		T38	5		T39	1
all_pins[5]	values[0x0]	332515	1			T1	1		T2	1		T3	1
all_pins[5]	values[0x1]	113	1			T20	5		T38	5		T39	2
all_pins[5]	transitions[0x0=>0x1]	83	1			T20	2		T38	4		T39	1
all_pins[5]	transitions[0x1=>0x0]	73	1			T20	1		T30	5		T38	3
all_pins[6]	values[0x0]	332525	1			T1	1		T2	1		T3	1
all_pins[6]	values[0x1]	103	1			T20	4		T30	5		T38	4
all_pins[6]	transitions[0x0=>0x1]	77	1			T20	4		T30	5		T38	1
all_pins[6]	transitions[0x1=>0x0]	79	1			T20	1		T38	2		T39	2
all_pins[7]	values[0x0]	332523	1			T1	1		T2	1		T3	1
all_pins[7]	values[0x1]	105	1			T20	1		T38	5		T39	2
all_pins[7]	transitions[0x0=>0x1]	69	1			T20	1		T38	5		T39	1
all_pins[7]	transitions[0x1=>0x0]	88	1			T30	3		T38	1		T39	4