Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
63.01	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	54	74	57.81

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	54	74	57.81	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	468	1			T11	32		T83	4		T53	36
values[1]	384	1			T23	12		T131	10		T179	6
values[2]	540	1			T6	24		T9	24		T54	22
values[3]	460	1			T13	2		T128	2		T52	8
values[4]	402	1			T65	30		T180	2		T181	2
values[5]	372	1			T5	34		T44	22		T56	20
values[6]	440	1			T10	4		T41	24		T110	2
values[7]	394	1			T7	6		T82	10		T182	18

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	384	1			T44	22		T183	10		T184	18
values[1]	338	1			T83	4		T128	2		T23	12
values[2]	432	1			T7	6		T9	24		T65	30
values[3]	530	1			T5	34		T181	2		T56	20
values[4]	326	1			T11	32		T13	2		T42	14
values[5]	378	1			T6	24		T10	4		T110	2
values[6]	548	1			T52	8		T53	36		T131	10
values[7]	524	1			T41	24		T45	24		T54	22

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3410

1

T5

24

T6

24

T7

6

auto[1]

50

1

T5

10

T65

8

T53

4

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	54	74	57.81	54

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[2]]	[values[1]]	0	1	1
[auto[0]]	[values[4] , values[5]]	[values[4]]	--	--	2
[auto[0]]	[values[6]]	[values[2]]	0	1	1
[auto[1]]	[values[0]]	[values[0] , values[1] , values[2] , values[3] , values[4]]	--	--	5
[auto[1]]	[values[0]]	[values[7]]	0	1	1
[auto[1]]	[values[1]]	[values[0]]	0	1	1
[auto[1]]	[values[1]]	[values[2] , values[3] , values[4] , values[5] , values[6] , values[7]]	--	--	6
[auto[1]]	[values[2]]	[values[0] , values[1]]	--	--	2
[auto[1]]	[values[2]]	[values[4] , values[5] , values[6]]	--	--	3
[auto[1]]	[values[3]]	[values[0] , values[1] , values[2] , values[3] , values[4]]	--	--	5
[auto[1]]	[values[3]]	[values[6] , values[7]]	--	--	2
[auto[1]]	[values[4]]	[values[0]]	0	1	1
[auto[1]]	[values[4]]	[values[3] , values[4] , values[5] , values[6] , values[7]]	--	--	5
[auto[1]]	[values[5]]	[values[0] , values[1] , values[2]]	--	--	3
[auto[1]]	[values[5]]	[values[4] , values[5] , values[6] , values[7]]	--	--	4
[auto[1]]	[values[6]]	[values[1] , values[2] , values[3] , values[4] , values[5]]	--	--	5
[auto[1]]	[values[6]]	[values[7]]	0	1	1
[auto[1]]	[values[7]]	[values[0]]	0	1	1
[auto[1]]	[values[7]]	[values[2] , values[3] , values[4] , values[5] , values[6]]	--	--	5

Covered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	28	1			T185	6		T186	22		-	-
auto[0]	values[0]	values[1]	38	1			T83	4		T187	12		T188	12
auto[0]	values[0]	values[2]	26	1			T97	8		T189	8		T190	10
auto[0]	values[0]	values[3]	72	1			T191	22		T192	16		T193	6
auto[0]	values[0]	values[4]	90	1			T11	32		T194	8		T195	8
auto[0]	values[0]	values[5]	80	1			T74	22		T27	4		T196	20
auto[0]	values[0]	values[6]	72	1			T53	32		T197	16		T198	2
auto[0]	values[0]	values[7]	54	1			T199	12		T200	14		T201	8
auto[0]	values[1]	values[0]	48	1			T202	30		T203	18		-	-
auto[0]	values[1]	values[1]	76	1			T23	12		T179	6		T26	20
auto[0]	values[1]	values[2]	92	1			T177	12		T204	6		T205	14
auto[0]	values[1]	values[3]	8	1			T206	8		-	-		-	-
auto[0]	values[1]	values[4]	24	1			T207	18		T208	6		-	-
auto[0]	values[1]	values[5]	32	1			T170	10		T209	18		T210	4
auto[0]	values[1]	values[6]	60	1			T131	10		T211	8		T212	12
auto[0]	values[1]	values[7]	42	1			T213	8		T214	6		T215	20
auto[0]	values[2]	values[0]	58	1			T216	16		T217	14		T218	14
auto[0]	values[2]	values[2]	122	1			T9	24		T219	2		T220	36
auto[0]	values[2]	values[3]	110	1			T66	34		T104	8		T178	14
auto[0]	values[2]	values[4]	30	1			T221	18		T222	12		-	-
auto[0]	values[2]	values[5]	84	1			T6	24		T25	12		T223	24
auto[0]	values[2]	values[6]	58	1			T75	28		T224	2		T225	28
auto[0]	values[2]	values[7]	72	1			T54	22		T68	22		T226	28
auto[0]	values[3]	values[0]	32	1			T184	18		T227	6		T228	8
auto[0]	values[3]	values[1]	30	1			T128	2		T43	10		T229	18
auto[0]	values[3]	values[2]	88	1			T230	34		T231	26		T232	20
auto[0]	values[3]	values[3]	104	1			T233	14		T234	14		T235	20
auto[0]	values[3]	values[4]	30	1			T13	2		T236	24		T237	4
auto[0]	values[3]	values[5]	54	1			T238	16		T239	14		T240	24
auto[0]	values[3]	values[6]	48	1			T52	8		T241	12		T112	24
auto[0]	values[3]	values[7]	72	1			T242	14		T24	18		T243	4
auto[0]	values[4]	values[0]	56	1			T244	6		T245	26		T246	24
auto[0]	values[4]	values[1]	100	1			T247	10		T248	28		T249	20
auto[0]	values[4]	values[2]	40	1			T65	22		T250	14		T251	4
auto[0]	values[4]	values[3]	20	1			T181	2		T252	8		T253	10
auto[0]	values[4]	values[5]	20	1			T180	2		T254	6		T105	4
auto[0]	values[4]	values[6]	90	1			T255	6		T256	10		T107	16
auto[0]	values[4]	values[7]	66	1			T176	12		T257	10		T258	18
auto[0]	values[5]	values[0]	56	1			T44	22		T183	10		T259	24
auto[0]	values[5]	values[1]	6	1			T260	6		-	-		-	-
auto[0]	values[5]	values[2]	4	1			T261	4		-	-		-	-
auto[0]	values[5]	values[3]	142	1			T5	24		T56	20		T262	38
auto[0]	values[5]	values[5]	66	1			T263	18		T264	4		T265	18
auto[0]	values[5]	values[6]	44	1			T46	16		T266	2		T267	26
auto[0]	values[5]	values[7]	44	1			T268	30		T269	10		T270	4
auto[0]	values[6]	values[0]	80	1			T271	8		T113	10		T69	26
auto[0]	values[6]	values[1]	70	1			T272	22		T273	12		T274	10
auto[0]	values[6]	values[3]	20	1			T275	16		T276	4		-	-
auto[0]	values[6]	values[4]	58	1			T42	14		T277	16		T278	8
auto[0]	values[6]	values[5]	18	1			T10	4		T110	2		T279	12
auto[0]	values[6]	values[6]	90	1			T67	16		T280	4		T281	12
auto[0]	values[6]	values[7]	96	1			T41	24		T45	24		T282	4
auto[0]	values[7]	values[0]	22	1			T111	10		T283	12		-	-
auto[0]	values[7]	values[1]	12	1			T284	12		-	-		-	-
auto[0]	values[7]	values[2]	50	1			T7	6		T285	10		T286	34
auto[0]	values[7]	values[3]	42	1			T287	2		T288	12		T289	28
auto[0]	values[7]	values[4]	94	1			T84	14		T76	24		T290	14
auto[0]	values[7]	values[5]	18	1			T291	8		T292	10		-	-
auto[0]	values[7]	values[6]	78	1			T82	10		T293	20		T294	10
auto[0]	values[7]	values[7]	74	1			T182	18		T295	8		T296	8
auto[1]	values[0]	values[5]	4	1			T196	2		T72	2		-	-
auto[1]	values[0]	values[6]	4	1			T53	4		-	-		-	-
auto[1]	values[1]	values[1]	2	1			T70	2		-	-		-	-
auto[1]	values[2]	values[2]	2	1			T297	2		-	-		-	-
auto[1]	values[2]	values[3]	2	1			T66	2		-	-		-	-
auto[1]	values[2]	values[7]	2	1			T68	2		-	-		-	-
auto[1]	values[3]	values[5]	2	1			T240	2		-	-		-	-
auto[1]	values[4]	values[1]	2	1			T73	2		-	-		-	-
auto[1]	values[4]	values[2]	8	1			T65	8		-	-		-	-
auto[1]	values[5]	values[3]	10	1			T5	10		-	-		-	-
auto[1]	values[6]	values[0]	4	1			T69	2		T71	2		-	-
auto[1]	values[6]	values[6]	4	1			T67	4		-	-		-	-
auto[1]	values[7]	values[1]	2	1			T284	2		-	-		-	-
auto[1]	values[7]	values[7]	2	1			T298	2		-	-		-	-