Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1419

1

T1

11

T14

9

T15

5

auto[1]

1314

1

T1

11

T14

1

T15

8

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

746

1

T14

10

T19

17

T59

11

auto[1]

1987

1

T1

22

T15

13

T21

3

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2433

1

T1

22

T14

10

T15

13

auto[1]

300

1

T19

5

T59

4

T55

2

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	575	1			T1	5		T14	5		T15	2
valid[1]	546	1			T1	3		T14	4		T15	2
valid[2]	485	1			T1	5		T14	1		T15	2
valid[3]	582	1			T1	3		T15	4		T21	1
valid[4]	545	1			T1	6		T15	3		T19	4

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	42	1			T14	4		T19	1		T64	1
auto[0]	auto[0]	valid[0]	auto[1]	211	1			T1	4		T15	1		T21	1
auto[0]	auto[0]	valid[1]	auto[0]	61	1			T14	4		T19	3		T59	1
auto[0]	auto[0]	valid[1]	auto[1]	194	1			T22	1		T60	2		T93	1
auto[0]	auto[0]	valid[2]	auto[0]	53	1			T14	1		T59	1		T64	3
auto[0]	auto[0]	valid[2]	auto[1]	159	1			T1	2		T15	1		T93	1
auto[0]	auto[0]	valid[3]	auto[0]	44	1			T64	1		T90	1		T91	4
auto[0]	auto[0]	valid[3]	auto[1]	224	1			T1	1		T15	2		T22	1
auto[0]	auto[0]	valid[4]	auto[0]	44	1			T19	1		T59	1		T398	1
auto[0]	auto[0]	valid[4]	auto[1]	222	1			T1	4		T15	1		T60	2
auto[0]	auto[1]	valid[0]	auto[0]	43	1			T14	1		T19	1		T64	2
auto[0]	auto[1]	valid[0]	auto[1]	212	1			T1	1		T15	1		T60	1
auto[0]	auto[1]	valid[1]	auto[0]	28	1			T64	1		T90	2		T91	4
auto[0]	auto[1]	valid[1]	auto[1]	204	1			T1	3		T15	2		T21	1
auto[0]	auto[1]	valid[2]	auto[0]	43	1			T19	4		T59	1		T90	1
auto[0]	auto[1]	valid[2]	auto[1]	178	1			T1	3		T15	1		T58	1
auto[0]	auto[1]	valid[3]	auto[0]	50	1			T59	2		T55	2		T64	1
auto[0]	auto[1]	valid[3]	auto[1]	209	1			T1	2		T15	2		T21	1
auto[0]	auto[1]	valid[4]	auto[0]	38	1			T19	2		T59	1		T64	1
auto[0]	auto[1]	valid[4]	auto[1]	174	1			T1	2		T15	2		T60	1
auto[1]	auto[0]	valid[0]	auto[0]	34	1			T19	2		T55	1		T64	1
auto[1]	auto[0]	valid[1]	auto[0]	30	1			T90	1		T393	1		T382	2
auto[1]	auto[0]	valid[2]	auto[0]	30	1			T90	1		T91	1		T382	1
auto[1]	auto[0]	valid[3]	auto[0]	30	1			T59	1		T55	1		T64	2
auto[1]	auto[0]	valid[4]	auto[0]	41	1			T19	1		T59	1		T64	1
auto[1]	auto[1]	valid[0]	auto[0]	33	1			T19	1		T64	2		T90	1
auto[1]	auto[1]	valid[1]	auto[0]	29	1			T59	2		T64	1		T90	1
auto[1]	auto[1]	valid[2]	auto[0]	22	1			T64	2		T91	1		T382	2
auto[1]	auto[1]	valid[3]	auto[0]	25	1			T19	1		T90	1		T26	1
auto[1]	auto[1]	valid[4]	auto[0]	26	1			T91	1		T396	1		T381	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal