Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18625

1

T14

144

T16

9

T19

339

auto[1]

18832

1

T1

246

T15

13

T21

3

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30467

1

T1

246

T14

102

T15

13

auto[1]

6990

1

T14

42

T16

3

T19

123

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	19599	1			T1	129		T14	75		T15	13
others[1]	3167	1			T1	27		T14	12		T16	1
others[2]	3043	1			T1	18		T14	16		T16	1
others[3]	3554	1			T1	25		T14	13		T16	1
interest[1]	2069	1			T1	10		T14	9		T22	9
interest[4]	12918	1			T1	86		T14	48		T15	13
interest[64]	6025	1			T1	37		T14	19		T16	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	6026	1			T14	54		T16	3		T19	118
auto[0]	auto[0]	others[1]	1002	1			T14	9		T16	1		T19	15
auto[0]	auto[0]	others[2]	954	1			T14	11		T16	1		T19	17
auto[0]	auto[0]	others[3]	1087	1			T14	9		T16	1		T19	23
auto[0]	auto[0]	interest[1]	665	1			T14	7		T19	6		T59	12
auto[0]	auto[0]	interest[4]	3927	1			T14	37		T16	1		T19	75
auto[0]	auto[0]	interest[64]	1901	1			T14	12		T19	37		T59	38
auto[0]	auto[1]	others[0]	10036	1			T1	129		T15	13		T21	3
auto[0]	auto[1]	others[1]	1572	1			T1	27		T22	6		T59	4
auto[0]	auto[1]	others[2]	1487	1			T1	18		T22	5		T59	2
auto[0]	auto[1]	others[3]	1744	1			T1	25		T22	7		T59	2
auto[0]	auto[1]	interest[1]	1012	1			T1	10		T22	9		T59	5
auto[0]	auto[1]	interest[4]	6725	1			T1	86		T15	13		T21	3
auto[0]	auto[1]	interest[64]	2981	1			T1	37		T22	8		T59	5
auto[1]	auto[0]	others[0]	3537	1			T14	21		T16	1		T19	67
auto[1]	auto[0]	others[1]	593	1			T14	3		T19	9		T59	8
auto[1]	auto[0]	others[2]	602	1			T14	5		T19	11		T59	10
auto[1]	auto[0]	others[3]	723	1			T14	4		T19	17		T59	17
auto[1]	auto[0]	interest[1]	392	1			T14	2		T19	4		T59	8
auto[1]	auto[0]	interest[4]	2266	1			T14	11		T19	38		T59	42
auto[1]	auto[0]	interest[64]	1143	1			T14	7		T16	2		T19	15

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal