Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	492	1			T20	10		T30	14		T38	14
all_values[1]	492	1			T20	10		T30	14		T38	14
all_values[2]	492	1			T20	10		T30	14		T38	14
all_values[3]	492	1			T20	10		T30	14		T38	14
all_values[4]	492	1			T20	10		T30	14		T38	14
all_values[5]	492	1			T20	10		T30	14		T38	14
all_values[6]	492	1			T20	10		T30	14		T38	14
all_values[7]	492	1			T20	10		T30	14		T38	14

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2058

1

T20

44

T30

63

T38

57

auto[1]

1878

1

T20

36

T30

49

T38

55

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1560

1

T20

26

T30

59

T38

55

auto[1]

2376

1

T20

54

T30

53

T38

57

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2228

1

T20

40

T30

72

T38

72

auto[1]

1708

1

T20

40

T30

40

T38

40

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	98	1			T20	1		T30	5		T38	6
all_values[0]	auto[0]	auto[0]	auto[1]	67	1			T20	2		T30	2		T38	2
all_values[0]	auto[0]	auto[1]	auto[0]	76	1			T20	1		T30	1		T38	2
all_values[0]	auto[0]	auto[1]	auto[1]	29	1			T30	1		T39	2		T355	1
all_values[0]	auto[1]	auto[0]	auto[1]	119	1			T20	6		T30	3		T38	1
all_values[0]	auto[1]	auto[1]	auto[1]	103	1			T30	2		T38	3		T39	1
all_values[1]	auto[0]	auto[0]	auto[0]	83	1			T20	1		T38	2		T39	3
all_values[1]	auto[0]	auto[0]	auto[1]	47	1			T20	1		T30	1		T38	3
all_values[1]	auto[0]	auto[1]	auto[0]	93	1			T30	6		T38	4		T39	1
all_values[1]	auto[0]	auto[1]	auto[1]	51	1			T20	2		T30	2		T38	1
all_values[1]	auto[1]	auto[0]	auto[1]	100	1			T20	5		T38	1		T39	4
all_values[1]	auto[1]	auto[1]	auto[1]	118	1			T20	1		T30	5		T38	3
all_values[2]	auto[0]	auto[0]	auto[0]	105	1			T20	1		T30	5		T38	3
all_values[2]	auto[0]	auto[0]	auto[1]	41	1			T20	1		T30	1		T38	2
all_values[2]	auto[0]	auto[1]	auto[0]	71	1			T30	2		T38	2		T39	1
all_values[2]	auto[0]	auto[1]	auto[1]	58	1			T20	4		T38	2		T39	1
all_values[2]	auto[1]	auto[0]	auto[1]	114	1			T20	2		T30	6		T38	1
all_values[2]	auto[1]	auto[1]	auto[1]	103	1			T20	2		T38	4		T39	2
all_values[3]	auto[0]	auto[0]	auto[0]	82	1			T20	7		T30	6		T38	3
all_values[3]	auto[0]	auto[0]	auto[1]	48	1			T30	1		T38	1		T39	3
all_values[3]	auto[0]	auto[1]	auto[0]	90	1			T20	2		T30	3		T38	3
all_values[3]	auto[0]	auto[1]	auto[1]	62	1			T38	1		T39	1		T356	1
all_values[3]	auto[1]	auto[0]	auto[1]	111	1			T30	2		T38	5		T39	3
all_values[3]	auto[1]	auto[1]	auto[1]	99	1			T20	1		T30	2		T38	1
all_values[4]	auto[0]	auto[0]	auto[0]	104	1			T20	1		T30	4		T38	3
all_values[4]	auto[0]	auto[0]	auto[1]	44	1			T20	1		T38	1		T356	1
all_values[4]	auto[0]	auto[1]	auto[0]	70	1			T20	4		T30	5		T38	5
all_values[4]	auto[0]	auto[1]	auto[1]	51	1			T38	1		T39	4		T162	1
all_values[4]	auto[1]	auto[0]	auto[1]	109	1			T20	2		T30	1		T38	2
all_values[4]	auto[1]	auto[1]	auto[1]	114	1			T20	2		T30	4		T38	2
all_values[5]	auto[0]	auto[0]	auto[0]	138	1			T20	1		T30	7		T38	5
all_values[5]	auto[0]	auto[1]	auto[0]	134	1			T20	1		T30	4		T38	3
all_values[5]	auto[1]	auto[0]	auto[1]	116	1			T20	3		T30	2		T38	2
all_values[5]	auto[1]	auto[1]	auto[1]	104	1			T20	5		T30	1		T38	4
all_values[6]	auto[0]	auto[0]	auto[0]	107	1			T30	2		T38	3		T39	4
all_values[6]	auto[0]	auto[0]	auto[1]	46	1			T30	2		T39	1		T356	1
all_values[6]	auto[0]	auto[1]	auto[0]	97	1			T20	2		T30	2		T38	4
all_values[6]	auto[0]	auto[1]	auto[1]	40	1			T20	1		T30	1		T38	1
all_values[6]	auto[1]	auto[0]	auto[1]	119	1			T20	3		T30	3		T38	3
all_values[6]	auto[1]	auto[1]	auto[1]	83	1			T20	4		T30	4		T38	3
all_values[7]	auto[0]	auto[0]	auto[0]	107	1			T20	1		T30	4		T38	5
all_values[7]	auto[0]	auto[0]	auto[1]	45	1			T20	2		T30	2		T39	1
all_values[7]	auto[0]	auto[1]	auto[0]	105	1			T20	3		T30	3		T38	2
all_values[7]	auto[0]	auto[1]	auto[1]	39	1			T38	2		T162	2		T355	1
all_values[7]	auto[1]	auto[0]	auto[1]	108	1			T20	3		T30	4		T38	3
all_values[7]	auto[1]	auto[1]	auto[1]	88	1			T20	1		T30	1		T38	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal