Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	262855	1			T1	1		T2	1		T3	1
all_values[1]	262855	1			T1	1		T2	1		T3	1
all_values[2]	262855	1			T1	1		T2	1		T3	1
all_values[3]	262855	1			T1	1		T2	1		T3	1
all_values[4]	262855	1			T1	1		T2	1		T3	1
all_values[5]	262855	1			T1	1		T2	1		T3	1
all_values[6]	262855	1			T1	1		T2	1		T3	1
all_values[7]	262855	1			T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2100724

1

T1

8

T2

8

T3

8

auto[1]

2116

1

T36

170

T37

109

T38

27

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2100842

1

T1

8

T2

8

T3

8

auto[1]

1998

1

T64

5

T69

2

T65

16

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	262489	1			T1	1		T2	1		T3	1
all_values[0]	auto[0]	auto[1]	118	1			T36	15		T37	2		T38	4
all_values[0]	auto[1]	auto[0]	136	1			T36	13		T37	13		T45	2
all_values[0]	auto[1]	auto[1]	112	1			T36	7		T37	7		T45	1
all_values[1]	auto[0]	auto[0]	262498	1			T1	1		T2	1		T3	1
all_values[1]	auto[0]	auto[1]	112	1			T36	13		T37	4		T45	2
all_values[1]	auto[1]	auto[0]	131	1			T36	7		T37	9		T38	3
all_values[1]	auto[1]	auto[1]	114	1			T36	8		T37	2		T38	2
all_values[2]	auto[0]	auto[0]	262487	1			T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	107	1			T36	17		T37	5		T45	3
all_values[2]	auto[1]	auto[0]	148	1			T36	10		T37	7		T38	2
all_values[2]	auto[1]	auto[1]	113	1			T36	8		T37	4		T38	4
all_values[3]	auto[0]	auto[0]	262473	1			T1	1		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	119	1			T95	10		T313	2		T36	8
all_values[3]	auto[1]	auto[0]	164	1			T36	14		T37	7		T38	4
all_values[3]	auto[1]	auto[1]	99	1			T36	10		T37	6		T348	4
all_values[4]	auto[0]	auto[0]	262447	1			T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	123	1			T36	13		T37	7		T126	15
all_values[4]	auto[1]	auto[0]	172	1			T36	6		T37	12		T45	5
all_values[4]	auto[1]	auto[1]	113	1			T36	16		T37	3		T38	1
all_values[5]	auto[0]	auto[0]	262258	1			T1	1		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	329	1			T64	5		T69	2		T65	16
all_values[5]	auto[1]	auto[0]	185	1			T36	19		T37	9		T38	1
all_values[5]	auto[1]	auto[1]	83	1			T36	4		T37	2		T38	1
all_values[6]	auto[0]	auto[0]	262477	1			T1	1		T2	1		T3	1
all_values[6]	auto[0]	auto[1]	97	1			T36	5		T37	8		T38	1
all_values[6]	auto[1]	auto[0]	165	1			T36	21		T37	7		T38	5
all_values[6]	auto[1]	auto[1]	116	1			T36	6		T37	6		T45	3
all_values[7]	auto[0]	auto[0]	262476	1			T1	1		T2	1		T3	1
all_values[7]	auto[0]	auto[1]	114	1			T36	11		T37	7		T38	1
all_values[7]	auto[1]	auto[0]	136	1			T36	10		T37	6		T38	2
all_values[7]	auto[1]	auto[1]	129	1			T36	11		T37	9		T38	2