Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
71.31	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	1	37	97.37
Crosses	84	34	50	59.52

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	1	1	50.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	29	19	39.58	100	1	1	0
cr_modeXdummyXnum_lanes	36	5	31	86.11	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	1136	1			T2	8		T3	18		T6	2
auto[SpiFlashAddrCfg]	759	1			T4	2		T8	2		T90	4
auto[SpiFlashAddr3b]	1056	1			T3	8		T9	10		T66	14
auto[SpiFlashAddr4b]	864	1			T4	2		T9	6		T11	2

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2879

1

T2

8

T3

26

T6

2

auto[1]

936

1

T72

12

T73

26

T75

12

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2082

1

T2

6

T3

14

T6

2

auto[1]

1733

1

T2

2

T3

12

T8

2

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1418	1			T2	8		T3	18		T6	2
values[1]	85	1			T104	2		T297	5		T84	4
values[2]	148	1			T90	3		T73	10		T185	2
values[3]	252	1			T9	4		T72	2		T47	4
values[4]	238	1			T3	8		T9	6		T72	2
values[5]	182	1			T9	6		T72	2		T73	4
values[6]	136	1			T4	2		T66	2		T90	3
values[7]	178	1			T91	5		T92	2		T47	10
values[8]	1178	1			T4	2		T11	2		T66	8

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3316

1

T2

8

T3

26

T6

2

auto[1]

499

1

T9

16

T90

13

T91

5

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

3711

1

T2

8

T3

26

T6

2

write

104

1

T72

4

T73

4

T74

2

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

1927

1

T4

2

T9

10

T11

2

valids[0x1]

1888

1

T2

8

T3

26

T6

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	194	1			T2	6		T3	6		T4	2
internal_process_ops[0x5a]	174	1			T3	8		T66	4		T72	2
internal_process_ops[0x05]	242	1			T3	4		T66	2		T72	2
internal_process_ops[0x35]	148	1			T6	2		T102	4		T74	6
internal_process_ops[0x15]	134	1			T2	2		T3	8		T47	4
internal_process_ops[0x03]	236	1			T4	2		T8	2		T9	6
internal_process_ops[0x0b]	219	1			T90	4		T95	8		T31	2
internal_process_ops[0x3b]	326	1			T9	6		T72	2		T90	3
internal_process_ops[0x6b]	216	1			T9	4		T11	2		T90	3
internal_process_ops[0xbb]	283	1			T95	6		T166	3		T167	2
internal_process_ops[0xeb]	289	1			T4	2		T90	3		T91	5

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3765

1

T2

8

T3

26

T6

2

auto[1]

50

1

T72

4

T73

4

T76

2

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_upload

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3815

1

T2

8

T3

26

T6

2

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	29	19	39.58	29
Automatically Generated Cross Bins	48	29	19	39.58	29
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Element holes

cp_is_flash	cp_is_write	cp_addr_mode	cp_addr_swap_en	cp_payload_swap_en	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[write]	*	[auto[0]]	[auto[1]]	--	--	4
[auto[0]]	[write]	*	[auto[1]]	[auto[0]]	--	--	4
[auto[1]]	[read]	[auto[SpiFlashAddrDisabled]]	*	[auto[0]]	--	--	2
[auto[1]]	[write]	*	*	*	--	--	16

Uncovered bins

cp_is_flash	cp_is_write	cp_addr_mode	cp_addr_swap_en	cp_payload_swap_en	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[read]	[auto[SpiFlashAddrCfg] , auto[SpiFlashAddr3b] , auto[SpiFlashAddr4b]]	[auto[1]]	[auto[0]]	--	--	3

Covered bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

888

1

T2

8

T3

18

T6

2

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

218

1

T72

2

T75

8

T185

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

392

1

T4

2

T8

2

T31

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

182

1

T73

4

T75

2

T185

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

606

1

T3

8

T66

14

T92

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

262

1

T72

4

T73

18

T75

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

440

1

T4

2

T11

2

T66

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

224

1

T72

2

T185

2

T105

6

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

16

1

T188

4

T216

2

T206

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

14

1

T72

2

T76

2

T78

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

14

1

T74

2

T28

2

T254

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

16

1

T84

8

T86

2

T259

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

22

1

T190

4

T283

2

T254

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

10

1

T72

2

T73

4

T85

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2

1

T206

2

-

-

-

-

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

10

1

T250

4

T295

2

T296

4

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

155

1

T90

4

T91

5

T95

11

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

156

1

T9

10

T90

3

T95

8

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

188

1

T9

6

T90

6

T95

6

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	5	31	86.11	5

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Uncovered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[1]]	[valids[0x0]]	0	1	1
[auto[1]]	[values[0] , values[1]]	[valids[0x0]]	--	--	2
[auto[1]]	[values[2]]	[valids[0x1]]	0	1	1
[auto[1]]	[values[6]]	[valids[0x1]]	0	1	1

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	328	1			T66	6		T31	4		T28	4
auto[0]	values[0]	valids[0x1]	1046	1			T2	8		T3	18		T6	2
auto[0]	values[1]	valids[0x1]	74	1			T104	2		T84	4		T85	4
auto[0]	values[2]	valids[0x0]	98	1			T73	10		T185	2		T29	6
auto[0]	values[2]	valids[0x1]	24	1			T128	4		T243	4		T298	2
auto[0]	values[3]	valids[0x0]	126	1			T72	2		T47	4		T105	4
auto[0]	values[3]	valids[0x1]	78	1			T129	6		T203	4		T76	6
auto[0]	values[4]	valids[0x0]	110	1			T72	2		T74	2		T188	2
auto[0]	values[4]	valids[0x1]	76	1			T3	8		T28	2		T188	2
auto[0]	values[5]	valids[0x0]	98	1			T73	4		T74	8		T188	4
auto[0]	values[5]	valids[0x1]	40	1			T72	2		T82	2		T31	2
auto[0]	values[6]	valids[0x0]	90	1			T66	2		T74	4		T128	2
auto[0]	values[6]	valids[0x1]	34	1			T4	2		T73	4		T216	4
auto[0]	values[7]	valids[0x0]	90	1			T92	2		T47	10		T216	2
auto[0]	values[7]	valids[0x1]	48	1			T281	2		T249	2		T62	4
auto[0]	values[8]	valids[0x0]	650	1			T4	2		T11	2		T66	2
auto[0]	values[8]	valids[0x1]	306	1			T66	6		T92	2		T47	2
auto[1]	values[0]	valids[0x1]	44	1			T95	8		T299	5		T300	8
auto[1]	values[1]	valids[0x1]	11	1			T297	5		T301	6		-	-
auto[1]	values[2]	valids[0x0]	26	1			T90	3		T126	3		T302	6
auto[1]	values[3]	valids[0x0]	39	1			T9	4		T167	2		T303	10
auto[1]	values[3]	valids[0x1]	9	1			T303	4		T304	5		-	-
auto[1]	values[4]	valids[0x0]	37	1			T95	3		T305	2		T126	6
auto[1]	values[4]	valids[0x1]	15	1			T9	6		T90	4		T305	5
auto[1]	values[5]	valids[0x0]	37	1			T9	6		T299	9		T305	3
auto[1]	values[5]	valids[0x1]	7	1			T306	5		T307	2		-	-
auto[1]	values[6]	valids[0x0]	12	1			T90	3		T308	6		T309	3
auto[1]	values[7]	valids[0x0]	32	1			T91	5		T303	1		T310	12
auto[1]	values[7]	valids[0x1]	8	1			T311	5		T312	3		-	-
auto[1]	values[8]	valids[0x0]	154	1			T90	3		T95	10		T166	3
auto[1]	values[8]	valids[0x1]	68	1			T95	4		T310	8		T313	3