Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg
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Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
36.36 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv


Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 16 2 14 87.50
Crosses 72 54 18 25.00


Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_busy_bit 2 1 1 50.00 100 1 1 2
cp_is_host_read 2 0 2 100.00 100 1 1 2
cp_other_status 8 0 8 100.00 100 1 1 8
cp_sw_read_while_csb_active 2 0 2 100.00 100 1 1 2
cp_wel_bit 2 1 1 50.00 100 1 1 2


Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all_except_csb 64 48 16 25.00 100 1 1 0
cr_busyXwelXcsb 8 6 2 25.00 100 1 1 0


Summary for Variable cp_busy_bit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_busy_bit

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1844789 1 T2 1461 T3 26636 T6 593


Summary for Variable cp_is_host_read

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_is_host_read

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1673005 1 T2 949 T3 16268 T6 593
auto[1] 171784 1 T2 512 T3 10368 T47 1024


Summary for Variable cp_other_status

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 8 0 8 100.00


Automatically Generated Bins for cp_other_status

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:524287] 432383 1 T2 300 T3 7149 T6 2
auto[524288:1048575] 199073 1 T2 142 T3 2303 T8 5836
auto[1048576:1572863] 177282 1 T2 659 T3 1274 T4 10
auto[1572864:2097151] 197279 1 T2 224 T3 2669 T4 11
auto[2097152:2621439] 228160 1 T2 3 T3 3619 T6 107
auto[2621440:3145727] 200349 1 T3 1722 T6 182 T4 24
auto[3145728:3670015] 187181 1 T3 4161 T6 193 T9 1631
auto[3670016:4194303] 223082 1 T2 133 T3 3739 T6 109


Summary for Variable cp_sw_read_while_csb_active

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_sw_read_while_csb_active

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 185878 1 T2 535 T3 10680 T6 7
auto[1] 1658911 1 T2 926 T3 15956 T6 586


Summary for Variable cp_wel_bit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_wel_bit

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1844789 1 T2 1461 T3 26636 T6 593


Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 48 16 25.00 48


Automatically Generated Cross Bins for cr_all_except_csb

Element holes
cp_busy_bitcp_wel_bitcp_other_statuscp_is_host_readCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[1]] * * -- -- 16
[auto[1]] * * * -- -- 32


Covered bins
cp_busy_bitcp_wel_bitcp_other_statuscp_is_host_readCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0:524287] auto[0] 309695 1 T2 300 T3 3185 T6 2
auto[0] auto[0] auto[0:524287] auto[1] 122688 1 T3 3964 T47 168 T96 512
auto[0] auto[0] auto[524288:1048575] auto[0] 193424 1 T2 142 T3 2302 T8 5836
auto[0] auto[0] auto[524288:1048575] auto[1] 5649 1 T3 1 T180 252 T181 35
auto[0] auto[0] auto[1048576:1572863] auto[0] 168144 1 T2 147 T3 1027 T4 10
auto[0] auto[0] auto[1048576:1572863] auto[1] 9138 1 T2 512 T3 247 T47 257
auto[0] auto[0] auto[1572864:2097151] auto[0] 195246 1 T2 224 T3 2659 T4 11
auto[0] auto[0] auto[1572864:2097151] auto[1] 2033 1 T3 10 T47 512 T181 1317
auto[0] auto[0] auto[2097152:2621439] auto[0] 213080 1 T2 3 T3 2427 T6 107
auto[0] auto[0] auto[2097152:2621439] auto[1] 15080 1 T3 1192 T47 87 T180 3
auto[0] auto[0] auto[2621440:3145727] auto[0] 199434 1 T3 1703 T6 182 T4 24
auto[0] auto[0] auto[2621440:3145727] auto[1] 915 1 T3 19 T180 272 T182 514
auto[0] auto[0] auto[3145728:3670015] auto[0] 180794 1 T3 1752 T6 193 T9 1631
auto[0] auto[0] auto[3145728:3670015] auto[1] 6387 1 T3 2409 T180 260 T183 727
auto[0] auto[0] auto[3670016:4194303] auto[0] 213188 1 T2 133 T3 1213 T6 109
auto[0] auto[0] auto[3670016:4194303] auto[1] 9894 1 T3 2526 T183 7 T181 9


Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 6 2 25.00 6


Automatically Generated Cross Bins for cr_busyXwelXcsb

Element holes
cp_busy_bitcp_wel_bitcp_sw_read_while_csb_activeCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[1]] * -- -- 2
[auto[1]] * * -- -- 4


Covered bins
cp_busy_bitcp_wel_bitcp_sw_read_while_csb_activeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] 185878 1 T2 535 T3 10680 T6 7
auto[0] auto[0] auto[1] 1658911 1 T2 926 T3 15956 T6 586

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