Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
75.34	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	36	92	71.88

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	36	92	71.88	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2380

1

T2

8

T3

26

T6

2

auto[1]

936

1

T72

12

T73

26

T75

12

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	574	1			T4	6		T74	34		T105	18
values[1]	322	1			T2	8		T11	2		T128	8
values[2]	404	1			T129	16		T80	2		T262	14
values[3]	356	1			T72	12		T92	8		T73	26
values[4]	392	1			T8	2		T188	26		T104	4
values[5]	452	1			T3	26		T6	2		T96	2
values[6]	386	1			T66	16		T47	20		T231	32
values[7]	430	1			T102	6		T185	6		T183	10

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	524	1			T73	26		T186	2		T77	26
values[1]	336	1			T11	2		T92	8		T102	6
values[2]	374	1			T66	16		T82	2		T262	14
values[3]	314	1			T47	20		T75	12		T243	20
values[4]	442	1			T185	6		T28	32		T129	16
values[5]	420	1			T3	26		T4	6		T72	12
values[6]	430	1			T31	28		T260	8		T231	32
values[7]	476	1			T2	8		T6	2		T8	2

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	36	92	71.88	36

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[values[1]]	0	1	1
[auto[0]]	[values[3]]	[values[2] , values[3]]	--	--	2
[auto[0]]	[values[6]]	[values[0]]	0	1	1
[auto[0]]	[values[7]]	[values[3] , values[4]]	--	--	2
[auto[0]]	[values[7]]	[values[6]]	0	1	1
[auto[1]]	[values[0]]	[values[3]]	0	1	1
[auto[1]]	[values[0]]	[values[5] , values[6]]	--	--	2
[auto[1]]	[values[1]]	[values[1] , values[2] , values[3] , values[4]]	--	--	4
[auto[1]]	[values[1]]	[values[7]]	0	1	1
[auto[1]]	[values[2]]	[values[0]]	0	1	1
[auto[1]]	[values[2]]	[values[2] , values[3]]	--	--	2
[auto[1]]	[values[2]]	[values[6]]	0	1	1
[auto[1]]	[values[3]]	[values[1]]	0	1	1
[auto[1]]	[values[3]]	[values[4]]	0	1	1
[auto[1]]	[values[3]]	[values[6]]	0	1	1
[auto[1]]	[values[4]]	[values[0] , values[1]]	--	--	2
[auto[1]]	[values[4]]	[values[5] , values[6] , values[7]]	--	--	3
[auto[1]]	[values[5]]	[values[2] , values[3]]	--	--	2
[auto[1]]	[values[5]]	[values[6] , values[7]]	--	--	2
[auto[1]]	[values[6]]	[values[1] , values[2]]	--	--	2
[auto[1]]	[values[6]]	[values[5] , values[6]]	--	--	2
[auto[1]]	[values[7]]	[values[5]]	0	1	1

Covered bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	114	1			T29	16		T189	32		T62	14
auto[0]	values[0]	values[2]	8	1			T234	8		-	-		-	-
auto[0]	values[0]	values[3]	22	1			T314	12		T315	10		-	-
auto[0]	values[0]	values[4]	86	1			T181	12		T316	26		T263	14
auto[0]	values[0]	values[5]	30	1			T4	6		T191	24		-	-
auto[0]	values[0]	values[6]	38	1			T260	8		T317	10		T122	20
auto[0]	values[0]	values[7]	96	1			T74	34		T282	20		T318	24
auto[0]	values[1]	values[0]	14	1			T252	14		-	-		-	-
auto[0]	values[1]	values[1]	58	1			T11	2		T26	20		T319	2
auto[0]	values[1]	values[2]	12	1			T215	12		-	-		-	-
auto[0]	values[1]	values[3]	46	1			T32	10		T235	10		T63	2
auto[0]	values[1]	values[4]	16	1			T320	4		T27	10		T321	2
auto[0]	values[1]	values[5]	34	1			T322	30		T219	4		-	-
auto[0]	values[1]	values[6]	34	1			T323	34		-	-		-	-
auto[0]	values[1]	values[7]	16	1			T2	8		T128	8		-	-
auto[0]	values[2]	values[0]	66	1			T200	24		T324	8		T325	34
auto[0]	values[2]	values[1]	14	1			T240	4		T255	10		-	-
auto[0]	values[2]	values[2]	48	1			T262	14		T220	30		T256	4
auto[0]	values[2]	values[3]	46	1			T267	16		T177	20		T326	10
auto[0]	values[2]	values[4]	24	1			T129	16		T283	8		-	-
auto[0]	values[2]	values[5]	24	1			T80	2		T273	18		T279	4
auto[0]	values[2]	values[6]	36	1			T184	8		T228	8		T123	8
auto[0]	values[2]	values[7]	44	1			T223	16		T327	28		-	-
auto[0]	values[3]	values[0]	8	1			T186	2		T227	6		-	-
auto[0]	values[3]	values[1]	40	1			T92	8		T204	6		T328	10
auto[0]	values[3]	values[4]	46	1			T25	16		T238	6		T224	24
auto[0]	values[3]	values[5]	72	1			T180	12		T216	32		T83	8
auto[0]	values[3]	values[6]	56	1			T31	28		T287	6		T237	12
auto[0]	values[3]	values[7]	14	1			T281	14		-	-		-	-
auto[0]	values[4]	values[0]	54	1			T188	26		T187	8		T261	12
auto[0]	values[4]	values[1]	28	1			T178	16		T329	8		T276	4
auto[0]	values[4]	values[2]	18	1			T248	12		T195	6		-	-
auto[0]	values[4]	values[3]	10	1			T330	10		-	-		-	-
auto[0]	values[4]	values[4]	28	1			T104	4		T290	24		-	-
auto[0]	values[4]	values[5]	28	1			T331	8		T232	20		-	-
auto[0]	values[4]	values[6]	80	1			T264	2		T211	2		T226	22
auto[0]	values[4]	values[7]	70	1			T8	2		T332	30		T253	26
auto[0]	values[5]	values[0]	52	1			T77	26		T206	22		T239	4
auto[0]	values[5]	values[1]	12	1			T333	6		T258	6		-	-
auto[0]	values[5]	values[2]	52	1			T82	2		T225	14		T208	16
auto[0]	values[5]	values[3]	66	1			T233	18		T249	24		T246	6
auto[0]	values[5]	values[4]	88	1			T28	32		T7	10		T334	30
auto[0]	values[5]	values[5]	34	1			T3	26		T96	2		T175	6
auto[0]	values[5]	values[6]	14	1			T236	4		T335	10		-	-
auto[0]	values[5]	values[7]	32	1			T6	2		T251	16		T336	14
auto[0]	values[6]	values[1]	2	1			T98	2		-	-		-	-
auto[0]	values[6]	values[2]	50	1			T66	16		T277	18		T197	4
auto[0]	values[6]	values[3]	30	1			T47	20		T337	6		T274	4
auto[0]	values[6]	values[4]	10	1			T230	10		-	-		-	-
auto[0]	values[6]	values[5]	58	1			T254	14		T338	10		T269	26
auto[0]	values[6]	values[6]	114	1			T231	32		T48	14		T100	22
auto[0]	values[6]	values[7]	6	1			T286	6		-	-		-	-
auto[0]	values[7]	values[0]	44	1			T30	22		T339	22		-	-
auto[0]	values[7]	values[1]	48	1			T102	6		T183	10		T190	14
auto[0]	values[7]	values[2]	82	1			T340	28		T101	16		T289	26
auto[0]	values[7]	values[5]	56	1			T242	4		T203	12		T266	6
auto[0]	values[7]	values[7]	52	1			T222	10		T214	14		T341	16
auto[1]	values[0]	values[0]	4	1			T298	2		T201	2		-	-
auto[1]	values[0]	values[1]	48	1			T105	18		T218	30		-	-
auto[1]	values[0]	values[2]	52	1			T247	26		T342	26		-	-
auto[1]	values[0]	values[4]	26	1			T294	26		-	-		-	-
auto[1]	values[0]	values[7]	50	1			T76	34		T87	16		-	-
auto[1]	values[1]	values[0]	52	1			T79	26		T288	26		-	-
auto[1]	values[1]	values[5]	12	1			T58	12		-	-		-	-
auto[1]	values[1]	values[6]	28	1			T84	22		T173	6		-	-
auto[1]	values[2]	values[1]	38	1			T85	34		T209	4		-	-
auto[1]	values[2]	values[4]	40	1			T272	28		T343	12		-	-
auto[1]	values[2]	values[5]	16	1			T88	16		-	-		-	-
auto[1]	values[2]	values[7]	8	1			T196	8		-	-		-	-
auto[1]	values[3]	values[0]	26	1			T73	26		-	-		-	-
auto[1]	values[3]	values[2]	24	1			T205	24		-	-		-	-
auto[1]	values[3]	values[3]	28	1			T75	12		T344	16		-	-
auto[1]	values[3]	values[5]	12	1			T72	12		-	-		-	-
auto[1]	values[3]	values[7]	30	1			T295	30		-	-		-	-
auto[1]	values[4]	values[2]	20	1			T78	20		-	-		-	-
auto[1]	values[4]	values[3]	24	1			T296	24		-	-		-	-
auto[1]	values[4]	values[4]	32	1			T241	6		T244	26		-	-
auto[1]	values[5]	values[0]	10	1			T293	10		-	-		-	-
auto[1]	values[5]	values[1]	30	1			T198	30		-	-		-	-
auto[1]	values[5]	values[4]	18	1			T280	18		-	-		-	-
auto[1]	values[5]	values[5]	44	1			T217	28		T210	16		-	-
auto[1]	values[6]	values[0]	54	1			T86	26		T292	16		T345	12
auto[1]	values[6]	values[3]	22	1			T193	22		-	-		-	-
auto[1]	values[6]	values[4]	22	1			T285	22		-	-		-	-
auto[1]	values[6]	values[7]	18	1			T346	18		-	-		-	-
auto[1]	values[7]	values[0]	26	1			T347	14		T229	12		-	-
auto[1]	values[7]	values[1]	18	1			T89	18		-	-		-	-
auto[1]	values[7]	values[2]	8	1			T265	8		-	-		-	-
auto[1]	values[7]	values[3]	20	1			T243	20		-	-		-	-
auto[1]	values[7]	values[4]	6	1			T185	6		-	-		-	-
auto[1]	values[7]	values[6]	30	1			T259	30		-	-		-	-
auto[1]	values[7]	values[7]	40	1			T284	20		T250	20		-	-