Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	100	1			T11	2		T180	2		T129	8
auto[ReadAddrCrossIntoMailbox]	26	1			T128	2		T273	6		T200	6
auto[ReadAddrCrossOutOfMailbox]	20	1			T242	2		T262	2		T273	2
auto[ReadAddrCrossAllMailbox]	46	1			T8	2		T128	2		T262	2
auto[ReadAddrOutsideMailbox]	864	1			T4	4		T72	2		T92	4

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

528

1

T4

2

T8

1

T11

1

auto[1]

528

1

T4

2

T8

1

T11

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	146	1			T4	2		T8	2		T73	4
read_ops[0x0b]	140	1			T31	2		T28	2		T129	4
read_ops[0x3b]	230	1			T72	2		T73	4		T74	6
read_ops[0x6b]	160	1			T11	2		T92	2		T47	10
read_ops[0xbb]	204	1			T77	6		T29	2		T188	2
read_ops[0xeb]	176	1			T4	2		T92	2		T47	4

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	7	1			T129	1		T236	1		T291	3
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	7	1			T129	1		T236	1		T291	3
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	1	1			T128	1		-	-		-	-
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	1	1			T128	1		-	-		-	-
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	2	1			T262	1		T291	1		-	-
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	2	1			T262	1		T291	1		-	-
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	6	1			T8	1		T128	1		T262	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	6	1			T8	1		T128	1		T262	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	57	1			T4	1		T73	2		T30	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	57	1			T4	1		T73	2		T30	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	6	1			T129	2		T203	2		T273	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	6	1			T129	2		T203	2		T273	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	3	1			T273	1		T278	1		T329	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	3	1			T273	1		T278	1		T329	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	2	1			T291	1		T94	1		-	-
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	2	1			T291	1		T94	1		-	-
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	3	1			T273	2		T94	1		-	-
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	3	1			T273	2		T94	1		-	-
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	56	1			T31	1		T28	1		T104	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	56	1			T31	1		T28	1		T104	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	6	1			T100	1		T325	4		T256	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	6	1			T100	1		T325	4		T256	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	2	1			T200	1		T369	1		-	-
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	2	1			T200	1		T369	1		-	-
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	1	1			T200	1		-	-		-	-
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	1	1			T200	1		-	-		-	-
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	1	1			T369	1		-	-		-	-
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	1	1			T369	1		-	-		-	-
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	105	1			T72	1		T73	2		T74	3
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	105	1			T72	1		T73	2		T74	3
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	9	1			T11	1		T129	1		T203	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	9	1			T11	1		T129	1		T203	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	2	1			T273	1		T228	1		-	-
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	2	1			T273	1		T228	1		-	-
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	1	1			T192	1		-	-		-	-
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	1	1			T192	1		-	-		-	-
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	3	1			T200	2		T192	1		-	-
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	3	1			T200	2		T192	1		-	-
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	65	1			T92	1		T47	5		T105	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	65	1			T92	1		T47	5		T105	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	10	1			T200	2		T236	1		T278	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	10	1			T200	2		T236	1		T278	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	4	1			T200	2		T278	1		T192	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	4	1			T200	2		T278	1		T192	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	1	1			T321	1		-	-		-	-
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	1	1			T321	1		-	-		-	-
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	6	1			T200	2		T228	1		T278	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	6	1			T200	2		T228	1		T278	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	81	1			T77	3		T29	1		T188	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	81	1			T77	3		T29	1		T188	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	12	1			T180	1		T100	1		T287	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	12	1			T180	1		T100	1		T287	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	1	1			T273	1		-	-		-	-
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	1	1			T273	1		-	-		-	-
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	3	1			T242	1		T273	1		T287	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	3	1			T242	1		T273	1		T287	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	4	1			T287	1		T331	1		T341	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	4	1			T287	1		T331	1		T341	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	68	1			T4	1		T92	1		T47	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	68	1			T4	1		T92	1		T47	2