Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	262855	1			T1	1		T2	1		T3	1
all_pins[1]	262855	1			T1	1		T2	1		T3	1
all_pins[2]	262855	1			T1	1		T2	1		T3	1
all_pins[3]	262855	1			T1	1		T2	1		T3	1
all_pins[4]	262855	1			T1	1		T2	1		T3	1
all_pins[5]	262855	1			T1	1		T2	1		T3	1
all_pins[6]	262855	1			T1	1		T2	1		T3	1
all_pins[7]	262855	1			T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2101961	1			T1	8		T2	8		T3	8
values[0x1]	879	1			T36	70		T37	39		T38	10
transitions[0x0=>0x1]	653	1			T36	55		T37	33		T38	7
transitions[0x1=>0x0]	661	1			T36	55		T37	33		T38	7

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	262743	1			T1	1		T2	1		T3	1
all_pins[0]	values[0x1]	112	1			T36	7		T37	7		T45	1
all_pins[0]	transitions[0x0=>0x1]	83	1			T36	4		T37	5		T45	1
all_pins[0]	transitions[0x1=>0x0]	85	1			T36	5		T38	2		T45	1
all_pins[1]	values[0x0]	262741	1			T1	1		T2	1		T3	1
all_pins[1]	values[0x1]	114	1			T36	8		T37	2		T38	2
all_pins[1]	transitions[0x0=>0x1]	80	1			T36	7		T37	2		T45	1
all_pins[1]	transitions[0x1=>0x0]	79	1			T36	7		T37	4		T38	2
all_pins[2]	values[0x0]	262742	1			T1	1		T2	1		T3	1
all_pins[2]	values[0x1]	113	1			T36	8		T37	4		T38	4
all_pins[2]	transitions[0x0=>0x1]	85	1			T36	5		T37	4		T38	4
all_pins[2]	transitions[0x1=>0x0]	71	1			T36	7		T37	6		T348	3
all_pins[3]	values[0x0]	262756	1			T1	1		T2	1		T3	1
all_pins[3]	values[0x1]	99	1			T36	10		T37	6		T348	4
all_pins[3]	transitions[0x0=>0x1]	76	1			T36	7		T37	6		T348	1
all_pins[3]	transitions[0x1=>0x0]	90	1			T36	13		T37	3		T38	1
all_pins[4]	values[0x0]	262742	1			T1	1		T2	1		T3	1
all_pins[4]	values[0x1]	113	1			T36	16		T37	3		T38	1
all_pins[4]	transitions[0x0=>0x1]	89	1			T36	15		T37	3		T348	6
all_pins[4]	transitions[0x1=>0x0]	59	1			T36	3		T37	2		T45	2
all_pins[5]	values[0x0]	262772	1			T1	1		T2	1		T3	1
all_pins[5]	values[0x1]	83	1			T36	4		T37	2		T38	1
all_pins[5]	transitions[0x0=>0x1]	66	1			T36	4		T37	2		T38	1
all_pins[5]	transitions[0x1=>0x0]	99	1			T36	6		T37	6		T45	2
all_pins[6]	values[0x0]	262739	1			T1	1		T2	1		T3	1
all_pins[6]	values[0x1]	116	1			T36	6		T37	6		T45	3
all_pins[6]	transitions[0x0=>0x1]	84	1			T36	5		T37	3		T45	3
all_pins[6]	transitions[0x1=>0x0]	97	1			T36	10		T37	6		T38	2
all_pins[7]	values[0x0]	262726	1			T1	1		T2	1		T3	1
all_pins[7]	values[0x1]	129	1			T36	11		T37	9		T38	2
all_pins[7]	transitions[0x0=>0x1]	90	1			T36	8		T37	8		T38	2
all_pins[7]	transitions[0x1=>0x0]	81	1			T36	4		T37	6		T45	1