Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
65.07	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	51	77	60.16

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	51	77	60.16	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	270	1			T11	2		T30	22		T184	8
values[1]	450	1			T2	8		T185	6		T28	32
values[2]	374	1			T6	2		T128	8		T180	12
values[3]	612	1			T92	8		T75	12		T183	10
values[4]	490	1			T3	26		T8	2		T96	2
values[5]	440	1			T47	20		T73	26		T186	2
values[6]	318	1			T102	6		T82	2		T31	28
values[7]	362	1			T4	6		T66	16		T72	12

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	396	1			T128	8		T104	4		T187	8
values[1]	386	1			T3	26		T96	2		T74	34
values[2]	512	1			T66	16		T82	2		T31	28
values[3]	432	1			T4	6		T11	2		T47	20
values[4]	242	1			T180	12		T188	26		T81	14
values[5]	446	1			T72	12		T92	8		T102	6
values[6]	508	1			T2	8		T6	2		T8	2
values[7]	394	1			T185	6		T189	32		T190	14

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3266

1

T2

8

T3

26

T6

2

auto[1]

50

1

T72

4

T73

4

T76

2

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	51	77	60.16	51

Automatically Generated Cross Bins for cr_all

Element holes

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[1] , values[2]]	*	--	--	16

Uncovered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[values[2]]	0	1	1
[auto[0]]	[values[0]]	[values[5]]	0	1	1
[auto[1]]	[values[0]]	[values[1] , values[2] , values[3] , values[4] , values[5]]	--	--	5
[auto[1]]	[values[0]]	[values[7]]	0	1	1
[auto[1]]	[values[3]]	[values[0] , values[1] , values[2] , values[3] , values[4]]	--	--	5
[auto[1]]	[values[3]]	[values[6] , values[7]]	--	--	2
[auto[1]]	[values[4]]	[values[0] , values[1]]	--	--	2
[auto[1]]	[values[4]]	[values[7]]	0	1	1
[auto[1]]	[values[5]]	[values[0]]	0	1	1
[auto[1]]	[values[5]]	[values[2]]	0	1	1
[auto[1]]	[values[5]]	[values[4]]	0	1	1
[auto[1]]	[values[5]]	[values[7]]	0	1	1
[auto[1]]	[values[6]]	[values[1] , values[2] , values[3] , values[4] , values[5] , values[6] , values[7]]	--	--	7
[auto[1]]	[values[7]]	[values[0] , values[1]]	--	--	2
[auto[1]]	[values[7]]	[values[3] , values[4]]	--	--	2
[auto[1]]	[values[7]]	[values[6] , values[7]]	--	--	2

Covered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	68	1			T58	12		T191	24		T87	14
auto[0]	values[0]	values[1]	24	1			T184	8		T175	6		T192	10
auto[0]	values[0]	values[3]	44	1			T11	2		T193	22		T194	16
auto[0]	values[0]	values[4]	20	1			T81	14		T195	6		-	-
auto[0]	values[0]	values[6]	42	1			T30	22		T196	8		T197	4
auto[0]	values[0]	values[7]	68	1			T63	2		T182	18		T198	30
auto[0]	values[1]	values[0]	38	1			T104	4		T187	8		T199	8
auto[0]	values[1]	values[1]	48	1			T80	2		T200	24		T201	2
auto[0]	values[1]	values[2]	128	1			T28	32		T29	16		T202	12
auto[0]	values[1]	values[3]	42	1			T203	12		T204	6		T205	24
auto[0]	values[1]	values[4]	48	1			T188	26		T206	22		-	-
auto[0]	values[1]	values[5]	36	1			T49	8		T207	12		T208	16
auto[0]	values[1]	values[6]	88	1			T2	8		T77	26		T209	4
auto[0]	values[1]	values[7]	22	1			T185	6		T210	16		-	-
auto[0]	values[2]	values[0]	28	1			T128	8		T211	2		T212	8
auto[0]	values[2]	values[1]	44	1			T213	18		T214	14		T215	12
auto[0]	values[2]	values[2]	104	1			T216	32		T217	28		T218	30
auto[0]	values[2]	values[3]	34	1			T219	4		T220	30		-	-
auto[0]	values[2]	values[4]	20	1			T180	12		T56	2		T221	6
auto[0]	values[2]	values[5]	50	1			T222	10		T223	16		T224	24
auto[0]	values[2]	values[6]	52	1			T6	2		T83	8		T225	14
auto[0]	values[2]	values[7]	42	1			T190	14		T226	22		T227	6
auto[0]	values[3]	values[0]	30	1			T228	8		T229	12		T230	10
auto[0]	values[3]	values[1]	90	1			T231	32		T232	20		T79	26
auto[0]	values[3]	values[2]	62	1			T233	18		T178	16		T234	8
auto[0]	values[3]	values[3]	88	1			T235	10		T236	4		T237	12
auto[0]	values[3]	values[4]	60	1			T238	6		T239	4		T240	4
auto[0]	values[3]	values[5]	104	1			T92	8		T75	12		T241	6
auto[0]	values[3]	values[6]	102	1			T183	10		T242	4		T243	20
auto[0]	values[3]	values[7]	74	1			T244	26		T245	26		T246	6
auto[0]	values[4]	values[0]	106	1			T247	26		T248	12		T249	24
auto[0]	values[4]	values[1]	90	1			T3	26		T96	2		T74	34
auto[0]	values[4]	values[2]	20	1			T84	14		T173	6		-	-
auto[0]	values[4]	values[3]	64	1			T105	18		T48	14		T250	16
auto[0]	values[4]	values[4]	48	1			T78	18		T251	16		T252	14
auto[0]	values[4]	values[5]	40	1			T89	14		T253	26		-	-
auto[0]	values[4]	values[6]	68	1			T8	2		T86	24		T254	14
auto[0]	values[4]	values[7]	34	1			T93	20		T255	10		T256	4
auto[0]	values[5]	values[0]	16	1			T62	14		T257	2		-	-
auto[0]	values[5]	values[1]	42	1			T123	8		T258	6		T259	28
auto[0]	values[5]	values[2]	28	1			T260	8		T261	12		T99	8
auto[0]	values[5]	values[3]	98	1			T47	20		T129	16		T262	14
auto[0]	values[5]	values[4]	14	1			T263	14		-	-		-	-
auto[0]	values[5]	values[5]	96	1			T73	22		T186	2		T264	2
auto[0]	values[5]	values[6]	68	1			T265	8		T266	6		T27	10
auto[0]	values[5]	values[7]	62	1			T267	16		T268	20		T269	26
auto[0]	values[6]	values[0]	26	1			T88	14		T270	12		-	-
auto[0]	values[6]	values[1]	24	1			T181	12		T271	12		-	-
auto[0]	values[6]	values[2]	70	1			T82	2		T31	28		T272	28
auto[0]	values[6]	values[3]	34	1			T273	18		T274	4		T275	12
auto[0]	values[6]	values[4]	4	1			T276	4		-	-		-	-
auto[0]	values[6]	values[5]	46	1			T102	6		T277	18		T278	12
auto[0]	values[6]	values[6]	36	1			T279	4		T94	14		T280	18
auto[0]	values[6]	values[7]	76	1			T189	32		T100	22		T281	14
auto[0]	values[7]	values[0]	80	1			T282	20		T283	8		T284	20
auto[0]	values[7]	values[1]	22	1			T285	22		-	-		-	-
auto[0]	values[7]	values[2]	90	1			T66	16		T76	32		T286	6
auto[0]	values[7]	values[3]	22	1			T4	6		T32	10		T287	6
auto[0]	values[7]	values[4]	26	1			T288	26		-	-		-	-
auto[0]	values[7]	values[5]	58	1			T72	8		T289	26		T290	24
auto[0]	values[7]	values[6]	42	1			T98	2		T291	24		T292	16
auto[0]	values[7]	values[7]	16	1			T101	16		-	-		-	-
auto[1]	values[0]	values[0]	2	1			T87	2		-	-		-	-
auto[1]	values[0]	values[6]	2	1			T293	2		-	-		-	-
auto[1]	values[3]	values[5]	2	1			T294	2		-	-		-	-
auto[1]	values[4]	values[2]	8	1			T84	8		-	-		-	-
auto[1]	values[4]	values[3]	4	1			T250	4		-	-		-	-
auto[1]	values[4]	values[4]	2	1			T78	2		-	-		-	-
auto[1]	values[4]	values[5]	4	1			T89	4		-	-		-	-
auto[1]	values[4]	values[6]	2	1			T86	2		-	-		-	-
auto[1]	values[5]	values[1]	2	1			T259	2		-	-		-	-
auto[1]	values[5]	values[3]	2	1			T85	2		-	-		-	-
auto[1]	values[5]	values[5]	6	1			T73	4		T295	2		-	-
auto[1]	values[5]	values[6]	6	1			T296	6		-	-		-	-
auto[1]	values[6]	values[0]	2	1			T88	2		-	-		-	-
auto[1]	values[7]	values[2]	2	1			T76	2		-	-		-	-
auto[1]	values[7]	values[5]	4	1			T72	4		-	-		-	-