Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1430

1

T1

12

T13

7

T15

8

auto[1]

1494

1

T1

20

T13

11

T15

15

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

666

1

T13

18

T15

18

T16

3

auto[1]

2258

1

T1

32

T15

5

T17

3

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2652

1

T1

32

T13

12

T15

15

auto[1]

272

1

T13

6

T15

8

T16

3

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	578	1			T1	7		T13	4		T15	8
valid[1]	581	1			T1	6		T13	3		T15	4
valid[2]	628	1			T1	10		T13	5		T15	4
valid[3]	564	1			T1	3		T13	2		T15	2
valid[4]	573	1			T1	6		T13	4		T15	5

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	43	1			T13	1		T15	2		T130	1
auto[0]	auto[0]	valid[0]	auto[1]	214	1			T1	2		T17	1		T18	2
auto[0]	auto[0]	valid[1]	auto[0]	43	1			T13	1		T15	1		T20	1
auto[0]	auto[0]	valid[1]	auto[1]	206	1			T1	1		T111	1		T396	2
auto[0]	auto[0]	valid[2]	auto[0]	53	1			T13	3		T15	1		T19	1
auto[0]	auto[0]	valid[2]	auto[1]	213	1			T1	4		T18	1		T112	1
auto[0]	auto[0]	valid[3]	auto[0]	37	1			T13	1		T20	1		T382	1
auto[0]	auto[0]	valid[3]	auto[1]	220	1			T1	2		T15	1		T18	2
auto[0]	auto[0]	valid[4]	auto[0]	43	1			T19	1		T20	1		T65	1
auto[0]	auto[0]	valid[4]	auto[1]	215	1			T1	3		T18	1		T21	1
auto[0]	auto[1]	valid[0]	auto[0]	41	1			T13	3		T15	3		T19	2
auto[0]	auto[1]	valid[0]	auto[1]	231	1			T1	5		T15	2		T17	1
auto[0]	auto[1]	valid[1]	auto[0]	24	1			T130	2		T388	1		T127	1
auto[0]	auto[1]	valid[1]	auto[1]	248	1			T1	5		T17	1		T18	1
auto[0]	auto[1]	valid[2]	auto[0]	30	1			T15	2		T20	1		T103	1
auto[0]	auto[1]	valid[2]	auto[1]	272	1			T1	6		T18	1		T21	1
auto[0]	auto[1]	valid[3]	auto[0]	32	1			T13	1		T19	1		T103	1
auto[0]	auto[1]	valid[3]	auto[1]	223	1			T1	1		T16	1		T21	3
auto[0]	auto[1]	valid[4]	auto[0]	48	1			T13	2		T15	1		T19	1
auto[0]	auto[1]	valid[4]	auto[1]	216	1			T1	3		T15	2		T21	2
auto[1]	auto[0]	valid[0]	auto[0]	24	1			T16	1		T65	1		T383	2
auto[1]	auto[0]	valid[1]	auto[0]	25	1			T15	1		T103	1		T130	1
auto[1]	auto[0]	valid[2]	auto[0]	33	1			T13	1		T383	1		T130	1
auto[1]	auto[0]	valid[3]	auto[0]	35	1			T383	3		T397	1		T372	1
auto[1]	auto[0]	valid[4]	auto[0]	26	1			T15	2		T19	1		T103	1
auto[1]	auto[1]	valid[0]	auto[0]	25	1			T15	1		T19	1		T20	2
auto[1]	auto[1]	valid[1]	auto[0]	35	1			T13	2		T15	2		T16	1
auto[1]	auto[1]	valid[2]	auto[0]	27	1			T13	1		T15	1		T103	3
auto[1]	auto[1]	valid[3]	auto[0]	17	1			T15	1		T16	1		T19	1
auto[1]	auto[1]	valid[4]	auto[0]	25	1			T13	2		T19	1		T20	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal