Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18318

1

T13

572

T15

537

T16

141

auto[1]

22540

1

T1

335

T15

115

T17

3

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34047

1

T1

335

T13

377

T15

443

auto[1]

6811

1

T13

195

T15

209

T16

68

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	21224	1			T1	157		T13	298		T15	329
others[1]	3431	1			T1	32		T13	43		T15	55
others[2]	3427	1			T1	33		T13	50		T15	67
others[3]	3752	1			T1	34		T13	54		T15	61
interest[1]	2266	1			T1	13		T13	21		T15	34
interest[4]	14029	1			T1	107		T13	193		T15	215
interest[64]	6758	1			T1	66		T13	106		T15	106

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	5963	1			T13	204		T15	176		T16	40
auto[0]	auto[0]	others[1]	971	1			T13	26		T15	29		T16	8
auto[0]	auto[0]	others[2]	937	1			T13	30		T15	27		T16	2
auto[0]	auto[0]	others[3]	1061	1			T13	38		T15	29		T16	6
auto[0]	auto[0]	interest[1]	651	1			T13	17		T15	18		T16	3
auto[0]	auto[0]	interest[4]	3903	1			T13	141		T15	121		T16	29
auto[0]	auto[0]	interest[64]	1924	1			T13	62		T15	49		T16	14
auto[0]	auto[1]	others[0]	11795	1			T1	157		T15	54		T17	3
auto[0]	auto[1]	others[1]	1870	1			T1	32		T15	10		T16	3
auto[0]	auto[1]	others[2]	1931	1			T1	33		T15	11		T16	3
auto[0]	auto[1]	others[3]	2034	1			T1	34		T15	14		T16	6
auto[0]	auto[1]	interest[1]	1224	1			T1	13		T15	2		T16	4
auto[0]	auto[1]	interest[4]	7805	1			T1	107		T15	31		T17	3
auto[0]	auto[1]	interest[64]	3686	1			T1	66		T15	24		T16	6
auto[1]	auto[0]	others[0]	3466	1			T13	94		T15	99		T16	30
auto[1]	auto[0]	others[1]	590	1			T13	17		T15	16		T16	6
auto[1]	auto[0]	others[2]	559	1			T13	20		T15	29		T16	9
auto[1]	auto[0]	others[3]	657	1			T13	16		T15	18		T16	8
auto[1]	auto[0]	interest[1]	391	1			T13	4		T15	14		T16	2
auto[1]	auto[0]	interest[4]	2321	1			T13	52		T15	63		T16	26
auto[1]	auto[0]	interest[64]	1148	1			T13	44		T15	33		T16	13

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal