Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	464	1			T36	40		T37	27		T38	4
all_values[1]	464	1			T36	40		T37	27		T38	4
all_values[2]	464	1			T36	40		T37	27		T38	4
all_values[3]	464	1			T36	40		T37	27		T38	4
all_values[4]	464	1			T36	40		T37	27		T38	4
all_values[5]	464	1			T36	40		T37	27		T38	4
all_values[6]	464	1			T36	40		T37	27		T38	4
all_values[7]	464	1			T36	40		T37	27		T38	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1977

1

T36

181

T37

121

T38

17

auto[1]

1735

1

T36

139

T37

95

T38

15

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1494

1

T36

123

T37

90

T38

14

auto[1]

2218

1

T36

197

T37

126

T38

18

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2148

1

T36

187

T37

124

T38

19

auto[1]

1564

1

T36

133

T37

92

T38

13

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	96	1			T36	6		T37	5		T45	1
all_values[0]	auto[0]	auto[0]	auto[1]	50	1			T36	6		T38	1		T45	2
all_values[0]	auto[0]	auto[1]	auto[0]	70	1			T36	7		T37	8		T45	1
all_values[0]	auto[0]	auto[1]	auto[1]	58	1			T36	8		T37	4		T45	1
all_values[0]	auto[1]	auto[0]	auto[1]	102	1			T36	7		T37	5		T38	3
all_values[0]	auto[1]	auto[1]	auto[1]	88	1			T36	6		T37	5		T45	1
all_values[1]	auto[0]	auto[0]	auto[0]	108	1			T36	9		T37	10		T38	2
all_values[1]	auto[0]	auto[0]	auto[1]	46	1			T36	7		T37	1		T45	1
all_values[1]	auto[0]	auto[1]	auto[0]	66	1			T36	3		T37	6		T45	2
all_values[1]	auto[0]	auto[1]	auto[1]	44	1			T36	2		T37	1		T38	1
all_values[1]	auto[1]	auto[0]	auto[1]	101	1			T36	10		T37	6		T45	3
all_values[1]	auto[1]	auto[1]	auto[1]	99	1			T36	9		T37	3		T38	1
all_values[2]	auto[0]	auto[0]	auto[0]	93	1			T36	7		T37	10		T45	2
all_values[2]	auto[0]	auto[0]	auto[1]	41	1			T36	4		T37	2		T45	3
all_values[2]	auto[0]	auto[1]	auto[0]	78	1			T36	4		T37	3		T348	4
all_values[2]	auto[0]	auto[1]	auto[1]	43	1			T36	3		T37	1		T38	2
all_values[2]	auto[1]	auto[0]	auto[1]	118	1			T36	14		T37	7		T45	1
all_values[2]	auto[1]	auto[1]	auto[1]	91	1			T36	8		T37	4		T38	2
all_values[3]	auto[0]	auto[0]	auto[0]	102	1			T36	9		T37	4		T38	1
all_values[3]	auto[0]	auto[0]	auto[1]	38	1			T36	5		T37	5		T348	2
all_values[3]	auto[0]	auto[1]	auto[0]	79	1			T36	7		T37	4		T38	1
all_values[3]	auto[0]	auto[1]	auto[1]	41	1			T36	3		T37	2		T171	2
all_values[3]	auto[1]	auto[0]	auto[1]	106	1			T36	7		T37	4		T38	2
all_values[3]	auto[1]	auto[1]	auto[1]	98	1			T36	9		T37	8		T348	3
all_values[4]	auto[0]	auto[0]	auto[0]	85	1			T36	3		T37	3		T38	2
all_values[4]	auto[0]	auto[0]	auto[1]	52	1			T36	8		T37	4		T348	2
all_values[4]	auto[0]	auto[1]	auto[0]	92	1			T36	3		T37	9		T38	1
all_values[4]	auto[0]	auto[1]	auto[1]	45	1			T36	4		T37	3		T348	2
all_values[4]	auto[1]	auto[0]	auto[1]	97	1			T36	11		T37	6		T45	2
all_values[4]	auto[1]	auto[1]	auto[1]	93	1			T36	11		T37	2		T38	1
all_values[5]	auto[0]	auto[0]	auto[0]	145	1			T36	16		T37	10		T38	1
all_values[5]	auto[0]	auto[1]	auto[0]	137	1			T36	11		T37	5		T38	2
all_values[5]	auto[1]	auto[0]	auto[1]	104	1			T36	8		T37	9		T348	3
all_values[5]	auto[1]	auto[1]	auto[1]	78	1			T36	5		T37	3		T38	1
all_values[6]	auto[0]	auto[0]	auto[0]	110	1			T36	12		T37	3		T38	1
all_values[6]	auto[0]	auto[0]	auto[1]	41	1			T36	2		T37	1		T45	2
all_values[6]	auto[0]	auto[1]	auto[0]	74	1			T36	13		T37	2		T38	2
all_values[6]	auto[0]	auto[1]	auto[1]	55	1			T36	2		T37	4		T45	1
all_values[6]	auto[1]	auto[0]	auto[1]	97	1			T36	6		T37	11		T38	1
all_values[6]	auto[1]	auto[1]	auto[1]	87	1			T36	5		T37	6		T45	2
all_values[7]	auto[0]	auto[0]	auto[0]	90	1			T36	8		T37	5		T38	1
all_values[7]	auto[0]	auto[0]	auto[1]	42	1			T36	6		T37	3		T348	2
all_values[7]	auto[0]	auto[1]	auto[0]	69	1			T36	5		T37	3		T45	1
all_values[7]	auto[0]	auto[1]	auto[1]	58	1			T36	4		T37	3		T38	1
all_values[7]	auto[1]	auto[0]	auto[1]	113	1			T36	10		T37	7		T38	2
all_values[7]	auto[1]	auto[1]	auto[1]	92	1			T36	7		T37	6		T348	8

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal