Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	267721	1			T1	1		T2	1		T3	1
all_values[1]	267721	1			T1	1		T2	1		T3	1
all_values[2]	267721	1			T1	1		T2	1		T3	1
all_values[3]	267721	1			T1	1		T2	1		T3	1
all_values[4]	267721	1			T1	1		T2	1		T3	1
all_values[5]	267721	1			T1	1		T2	1		T3	1
all_values[6]	267721	1			T1	1		T2	1		T3	1
all_values[7]	267721	1			T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2139250

1

T1

8

T2

8

T3

8

auto[1]

2518

1

T35

52

T42

39

T43

63

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2139467

1

T1

8

T2

8

T3

8

auto[1]

2301

1

T15

12

T16

6

T94

2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	267264	1			T1	1		T2	1		T3	1
all_values[0]	auto[0]	auto[1]	141	1			T35	2		T42	1		T43	2
all_values[0]	auto[1]	auto[0]	178	1			T35	6		T42	2		T43	6
all_values[0]	auto[1]	auto[1]	138	1			T35	3		T42	3		T43	5
all_values[1]	auto[0]	auto[0]	267284	1			T1	1		T2	1		T3	1
all_values[1]	auto[0]	auto[1]	140	1			T35	1		T42	3		T43	2
all_values[1]	auto[1]	auto[0]	157	1			T35	1		T43	7		T158	8
all_values[1]	auto[1]	auto[1]	140	1			T35	3		T42	4		T43	2
all_values[2]	auto[0]	auto[0]	267270	1			T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	106	1			T35	1		T42	1		T158	3
all_values[2]	auto[1]	auto[0]	205	1			T35	3		T42	3		T43	9
all_values[2]	auto[1]	auto[1]	140	1			T35	3		T42	4		T43	3
all_values[3]	auto[0]	auto[0]	267287	1			T1	1		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	150	1			T35	1		T42	3		T43	3
all_values[3]	auto[1]	auto[0]	163	1			T35	1		T43	2		T158	6
all_values[3]	auto[1]	auto[1]	121	1			T35	1		T42	1		T43	3
all_values[4]	auto[0]	auto[0]	267237	1			T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	131	1			T94	2		T35	3		T162	3
all_values[4]	auto[1]	auto[0]	175	1			T35	4		T43	1		T158	5
all_values[4]	auto[1]	auto[1]	178	1			T35	1		T42	3		T43	3
all_values[5]	auto[0]	auto[0]	267132	1			T1	1		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	290	1			T15	12		T16	6		T66	1
all_values[5]	auto[1]	auto[0]	182	1			T35	3		T42	5		T43	3
all_values[5]	auto[1]	auto[1]	117	1			T35	4		T42	2		T43	3
all_values[6]	auto[0]	auto[0]	267298	1			T1	1		T2	1		T3	1
all_values[6]	auto[0]	auto[1]	120	1			T35	1		T42	1		T158	4
all_values[6]	auto[1]	auto[0]	190	1			T35	5		T43	4		T158	8
all_values[6]	auto[1]	auto[1]	113	1			T35	4		T42	3		T43	1
all_values[7]	auto[0]	auto[0]	267277	1			T1	1		T2	1		T3	1
all_values[7]	auto[0]	auto[1]	123	1			T35	1		T43	1		T158	6
all_values[7]	auto[1]	auto[0]	168	1			T35	7		T42	6		T43	6
all_values[7]	auto[1]	auto[1]	153	1			T35	3		T42	3		T43	5