Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
73.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	1	37	97.37
Crosses	84	31	53	63.10

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	1	1	50.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	28	20	41.67	100	1	1	0
cr_modeXdummyXnum_lanes	36	3	33	91.67	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	1038	1			T1	2		T9	6		T11	14
auto[SpiFlashAddrCfg]	869	1			T2	2		T8	2		T9	8
auto[SpiFlashAddr3b]	947	1			T1	12		T2	2		T3	2
auto[SpiFlashAddr4b]	744	1			T5	2		T6	4		T31	6

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2856

1

T1

14

T2

4

T3

2

auto[1]

742

1

T5

2

T70

10

T52

20

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1931

1

T1

4

T8

2

T9

18

auto[1]

1667

1

T1

10

T2

4

T3

2

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1438	1			T1	8		T9	8		T11	14
values[1]	120	1			T9	2		T6	8		T71	6
values[2]	183	1			T9	2		T68	4		T77	2
values[3]	131	1			T9	2		T68	2		T75	2
values[4]	146	1			T9	2		T56	2		T97	9
values[5]	200	1			T6	10		T31	6		T45	4
values[6]	164	1			T1	4		T8	2		T5	2
values[7]	178	1			T68	2		T25	6		T52	6
values[8]	1038	1			T1	2		T2	4		T3	2

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3022

1

T1

14

T2

4

T3

2

auto[1]

576

1

T7

2

T94

7

T96

17

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

3506

1

T1

12

T2

4

T3

2

write

92

1

T1

2

T31

4

T52

2

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

1668

1

T1

6

T2

4

T3

2

valids[0x1]

1930

1

T1

8

T8

2

T9

14

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	180	1			T9	2		T45	4		T89	4
internal_process_ops[0x5a]	180	1			T11	6		T104	2		T79	6
internal_process_ops[0x05]	166	1			T31	4		T70	2		T52	2
internal_process_ops[0x35]	156	1			T9	2		T11	8		T70	2
internal_process_ops[0x15]	192	1			T11	6		T70	2		T45	6
internal_process_ops[0x03]	257	1			T6	8		T31	4		T68	2
internal_process_ops[0x0b]	262	1			T1	6		T9	2		T25	4
internal_process_ops[0x3b]	258	1			T1	2		T2	2		T6	6
internal_process_ops[0x6b]	245	1			T31	2		T94	1		T52	4
internal_process_ops[0xbb]	277	1			T2	2		T7	2		T9	2
internal_process_ops[0xeb]	243	1			T5	2		T6	4		T31	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3562

1

T1

14

T2

4

T3

2

auto[1]

36

1

T52

2

T73

2

T74

2

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_upload

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3598

1

T1

14

T2

4

T3

2

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	28	20	41.67	28
Automatically Generated Cross Bins	48	28	20	41.67	28
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Element holes

cp_is_flash	cp_is_write	cp_addr_mode	cp_addr_swap_en	cp_payload_swap_en	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[write]	*	[auto[0]]	[auto[1]]	--	--	4
[auto[0]]	[write]	*	[auto[1]]	[auto[0]]	--	--	4
[auto[1]]	[read]	*	[auto[1]]	[auto[0]]	--	--	4
[auto[1]]	[write]	*	*	*	--	--	16

Covered bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

810

1

T9

6

T11

14

T31

6

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

202

1

T70

6

T52

4

T57

4

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

478

1

T2

2

T8

2

T9

8

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

178

1

T57

4

T89

2

T137

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

564

1

T1

12

T2

2

T3

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

170

1

T70

4

T52

6

T89

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

372

1

T6

4

T31

2

T68

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

156

1

T5

2

T52

8

T57

6

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

8

1

T1

2

T278

4

T284

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

10

1

T52

2

T81

2

T83

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

22

1

T78

4

T173

2

T209

6

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

14

1

T84

2

T85

6

T87

6

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

6

1

T189

2

T227

2

T254

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

8

1

T74

2

T82

2

T87

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

20

1

T31

4

T262

2

T214

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

4

1

T73

2

T81

2

-

-

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

8

1

T285

8

-

-

-

-

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

177

1

T94

1

T97

7

T116

2

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

199

1

T7

2

T96

9

T116

16

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

192

1

T94

6

T96

8

T97

2

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	3	33	91.67	3

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Uncovered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[1]]	[valids[0x0]]	0	1	1
[auto[1]]	[values[0] , values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	314	1			T31	2		T70	4		T25	4
auto[0]	values[0]	valids[0x1]	1044	1			T1	8		T9	8		T11	14
auto[0]	values[1]	valids[0x1]	114	1			T9	2		T6	8		T71	6
auto[0]	values[2]	valids[0x0]	104	1			T68	4		T77	2		T104	2
auto[0]	values[2]	valids[0x1]	40	1			T9	2		T73	4		T231	4
auto[0]	values[3]	valids[0x0]	40	1			T9	2		T173	2		T227	2
auto[0]	values[3]	valids[0x1]	48	1			T68	2		T75	2		T78	2
auto[0]	values[4]	valids[0x0]	74	1			T56	2		T75	2		T107	4
auto[0]	values[4]	valids[0x1]	40	1			T9	2		T107	6		T231	2
auto[0]	values[5]	valids[0x0]	92	1			T6	10		T31	2		T45	4
auto[0]	values[5]	valids[0x1]	54	1			T31	4		T108	6		T209	2
auto[0]	values[6]	valids[0x0]	88	1			T1	4		T5	2		T187	4
auto[0]	values[6]	valids[0x1]	42	1			T8	2		T187	2		T46	2
auto[0]	values[7]	valids[0x0]	72	1			T25	6		T52	2		T137	2
auto[0]	values[7]	valids[0x1]	50	1			T68	2		T52	4		T80	2
auto[0]	values[8]	valids[0x0]	530	1			T1	2		T2	4		T3	2
auto[0]	values[8]	valids[0x1]	276	1			T11	6		T68	2		T25	2
auto[1]	values[0]	valids[0x1]	80	1			T94	3		T96	10		T160	8
auto[1]	values[1]	valids[0x1]	6	1			T163	6		-	-		-	-
auto[1]	values[2]	valids[0x0]	34	1			T116	6		T161	4		T286	5
auto[1]	values[2]	valids[0x1]	5	1			T287	5		-	-		-	-
auto[1]	values[3]	valids[0x0]	37	1			T288	4		T289	5		T290	4
auto[1]	values[3]	valids[0x1]	6	1			T286	6		-	-		-	-
auto[1]	values[4]	valids[0x0]	18	1			T97	2		T161	3		T288	5
auto[1]	values[4]	valids[0x1]	14	1			T97	7		T177	2		T291	5
auto[1]	values[5]	valids[0x0]	32	1			T96	5		T292	5		T293	1
auto[1]	values[5]	valids[0x1]	22	1			T294	3		T290	8		T295	8
auto[1]	values[6]	valids[0x0]	30	1			T116	1		T162	6		T296	3
auto[1]	values[6]	valids[0x1]	4	1			T285	4		-	-		-	-
auto[1]	values[7]	valids[0x0]	47	1			T116	9		T288	3		T297	5
auto[1]	values[7]	valids[0x1]	9	1			T298	9		-	-		-	-
auto[1]	values[8]	valids[0x0]	156	1			T7	2		T94	4		T96	2
auto[1]	values[8]	valids[0x1]	76	1			T161	3		T299	6		T296	1