Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg
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Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
36.36 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv


Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 16 2 14 87.50
Crosses 72 54 18 25.00


Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_busy_bit 2 1 1 50.00 100 1 1 2
cp_is_host_read 2 0 2 100.00 100 1 1 2
cp_other_status 8 0 8 100.00 100 1 1 8
cp_sw_read_while_csb_active 2 0 2 100.00 100 1 1 2
cp_wel_bit 2 1 1 50.00 100 1 1 2


Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all_except_csb 64 48 16 25.00 100 1 1 0
cr_busyXwelXcsb 8 6 2 25.00 100 1 1 0


Summary for Variable cp_busy_bit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_busy_bit

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1952601 1 T1 1 T2 2793 T3 1


Summary for Variable cp_is_host_read

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_is_host_read

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1826865 1 T1 1 T2 2793 T3 1
auto[1] 125736 1 T11 11232 T31 258 T45 1618


Summary for Variable cp_other_status

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 8 0 8 100.00


Automatically Generated Bins for cp_other_status

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:524287] 456885 1 T1 1 T2 1363 T3 1
auto[524288:1048575] 162253 1 T2 442 T7 222 T11 316
auto[1048576:1572863] 235961 1 T2 318 T7 363 T11 3094
auto[1572864:2097151] 256895 1 T11 177 T6 5012 T71 4299
auto[2097152:2621439] 241698 1 T7 241 T10 3 T11 1434
auto[2621440:3145727] 197560 1 T7 116 T11 1460 T6 934
auto[3145728:3670015] 206885 1 T2 333 T10 75 T11 1386
auto[3670016:4194303] 194464 1 T2 337 T7 1742 T11 2779


Summary for Variable cp_sw_read_while_csb_active

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_sw_read_while_csb_active

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 141072 1 T1 1 T2 367 T3 1
auto[1] 1811529 1 T2 2426 T7 7922 T10 75


Summary for Variable cp_wel_bit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_wel_bit

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1952601 1 T1 1 T2 2793 T3 1


Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 48 16 25.00 48


Automatically Generated Cross Bins for cr_all_except_csb

Element holes
cp_busy_bitcp_wel_bitcp_other_statuscp_is_host_readCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[1]] * * -- -- 16
[auto[1]] * * * -- -- 32


Covered bins
cp_busy_bitcp_wel_bitcp_other_statuscp_is_host_readCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0:524287] auto[0] 357850 1 T1 1 T2 1363 T3 1
auto[0] auto[0] auto[0:524287] auto[1] 99035 1 T11 7758 T31 258 T45 1075
auto[0] auto[0] auto[524288:1048575] auto[0] 159534 1 T2 442 T7 222 T11 306
auto[0] auto[0] auto[524288:1048575] auto[1] 2719 1 T11 10 T45 31 T106 1024
auto[0] auto[0] auto[1048576:1572863] auto[0] 232974 1 T2 318 T7 363 T11 830
auto[0] auto[0] auto[1048576:1572863] auto[1] 2987 1 T11 2264 T45 105 T182 354
auto[0] auto[0] auto[1572864:2097151] auto[0] 254434 1 T11 48 T6 5012 T71 4299
auto[0] auto[0] auto[1572864:2097151] auto[1] 2461 1 T11 129 T45 334 T91 1
auto[0] auto[0] auto[2097152:2621439] auto[0] 233370 1 T7 241 T10 3 T11 1429
auto[0] auto[0] auto[2097152:2621439] auto[1] 8328 1 T11 5 T45 68 T106 1652
auto[0] auto[0] auto[2621440:3145727] auto[0] 195490 1 T7 116 T11 1200 T6 934
auto[0] auto[0] auto[2621440:3145727] auto[1] 2070 1 T11 260 T45 4 T183 3
auto[0] auto[0] auto[3145728:3670015] auto[0] 201758 1 T2 333 T10 75 T11 1095
auto[0] auto[0] auto[3145728:3670015] auto[1] 5127 1 T11 291 T106 2279 T184 13
auto[0] auto[0] auto[3670016:4194303] auto[0] 191455 1 T2 337 T7 1742 T11 2264
auto[0] auto[0] auto[3670016:4194303] auto[1] 3009 1 T11 515 T45 1 T184 501


Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 6 2 25.00 6


Automatically Generated Cross Bins for cr_busyXwelXcsb

Element holes
cp_busy_bitcp_wel_bitcp_sw_read_while_csb_activeCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[1]] * -- -- 2
[auto[1]] * * -- -- 4


Covered bins
cp_busy_bitcp_wel_bitcp_sw_read_while_csb_activeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] 141072 1 T1 1 T2 367 T3 1
auto[0] auto[0] auto[1] 1811529 1 T2 2426 T7 7922 T10 75

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