Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
75.34	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	36	92	71.88

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	36	92	71.88	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2280

1

T1

14

T2

4

T3

2

auto[1]

742

1

T5

2

T70

10

T52

20

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	364	1			T75	18		T46	18		T185	8
values[1]	490	1			T5	2		T6	24		T25	22
values[2]	134	1			T1	14		T2	4		T235	10
values[3]	404	1			T3	2		T9	18		T31	18
values[4]	456	1			T11	20		T52	20		T56	14
values[5]	336	1			T68	22		T186	4		T257	12
values[6]	444	1			T57	14		T106	8		T117	20
values[7]	394	1			T8	2		T45	16		T29	12

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	420	1			T6	24		T71	16		T57	14
values[1]	416	1			T70	10		T105	4		T235	10
values[2]	374	1			T1	14		T9	18		T52	20
values[3]	450	1			T11	20		T80	14		T117	20
values[4]	388	1			T3	2		T68	22		T45	16
values[5]	382	1			T8	2		T89	16		T190	2
values[6]	254	1			T5	2		T31	18		T25	22
values[7]	338	1			T2	4		T79	28		T257	12

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	36	92	71.88	36

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[2]]	[values[5]]	0	1	1
[auto[0]]	[values[3]]	[values[3]]	0	1	1
[auto[0]]	[values[4]]	[values[5]]	0	1	1
[auto[0]]	[values[6]]	[values[6]]	0	1	1
[auto[1]]	[values[0]]	[values[0]]	0	1	1
[auto[1]]	[values[0]]	[values[2]]	0	1	1
[auto[1]]	[values[0]]	[values[5]]	0	1	1
[auto[1]]	[values[0]]	[values[7]]	0	1	1
[auto[1]]	[values[1]]	[values[0] , values[1]]	--	--	2
[auto[1]]	[values[1]]	[values[4] , values[5]]	--	--	2
[auto[1]]	[values[1]]	[values[7]]	0	1	1
[auto[1]]	[values[2]]	[values[0]]	0	1	1
[auto[1]]	[values[2]]	[values[2] , values[3] , values[4] , values[5] , values[6] , values[7]]	--	--	6
[auto[1]]	[values[3]]	[values[3]]	0	1	1
[auto[1]]	[values[3]]	[values[6] , values[7]]	--	--	2
[auto[1]]	[values[4]]	[values[5] , values[6] , values[7]]	--	--	3
[auto[1]]	[values[5]]	[values[0]]	0	1	1
[auto[1]]	[values[5]]	[values[2]]	0	1	1
[auto[1]]	[values[5]]	[values[4] , values[5]]	--	--	2
[auto[1]]	[values[5]]	[values[7]]	0	1	1
[auto[1]]	[values[6]]	[values[1] , values[2]]	--	--	2
[auto[1]]	[values[6]]	[values[7]]	0	1	1
[auto[1]]	[values[7]]	[values[6] , values[7]]	--	--	2

Covered bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	38	1			T278	26		T250	4		T300	8
auto[0]	values[0]	values[1]	54	1			T262	20		T124	12		T301	18
auto[0]	values[0]	values[2]	52	1			T302	6		T284	12		T195	20
auto[0]	values[0]	values[3]	10	1			T92	10		-	-		-	-
auto[0]	values[0]	values[4]	32	1			T46	18		T303	12		T249	2
auto[0]	values[0]	values[5]	40	1			T189	12		T304	28		-	-
auto[0]	values[0]	values[6]	8	1			T185	8		-	-		-	-
auto[0]	values[0]	values[7]	34	1			T261	16		T207	18		-	-
auto[0]	values[1]	values[0]	74	1			T6	24		T239	26		T223	24
auto[0]	values[1]	values[1]	18	1			T305	2		T306	16		-	-
auto[0]	values[1]	values[2]	30	1			T91	10		T122	12		T307	8
auto[0]	values[1]	values[3]	62	1			T192	2		T197	12		T259	26
auto[0]	values[1]	values[4]	14	1			T47	14		-	-		-	-
auto[0]	values[1]	values[5]	104	1			T190	2		T104	12		T173	30
auto[0]	values[1]	values[6]	24	1			T25	22		T308	2		-	-
auto[0]	values[1]	values[7]	86	1			T79	28		T182	6		T309	14
auto[0]	values[2]	values[0]	6	1			T310	4		T311	2		-	-
auto[0]	values[2]	values[1]	20	1			T235	10		T312	10		-	-
auto[0]	values[2]	values[2]	14	1			T1	14		-	-		-	-
auto[0]	values[2]	values[3]	28	1			T103	4		T313	6		T314	18
auto[0]	values[2]	values[4]	10	1			T241	2		T315	8		-	-
auto[0]	values[2]	values[6]	34	1			T267	22		T251	8		T316	4
auto[0]	values[2]	values[7]	4	1			T2	4		-	-		-	-
auto[0]	values[3]	values[0]	84	1			T71	16		T188	2		T266	18
auto[0]	values[3]	values[1]	22	1			T105	4		T258	14		T279	4
auto[0]	values[3]	values[2]	38	1			T9	18		T184	6		T317	10
auto[0]	values[3]	values[4]	54	1			T3	2		T109	16		T121	16
auto[0]	values[3]	values[5]	60	1			T187	6		T26	16		T269	4
auto[0]	values[3]	values[6]	18	1			T31	18		-	-		-	-
auto[0]	values[3]	values[7]	18	1			T212	2		T238	16		-	-
auto[0]	values[4]	values[0]	50	1			T77	16		T183	2		T107	26
auto[0]	values[4]	values[1]	42	1			T226	10		T263	2		T200	16
auto[0]	values[4]	values[2]	32	1			T318	32		-	-		-	-
auto[0]	values[4]	values[3]	76	1			T11	20		T254	28		T222	24
auto[0]	values[4]	values[4]	30	1			T56	14		T236	10		T274	6
auto[0]	values[4]	values[6]	14	1			T228	8		T319	6		-	-
auto[0]	values[4]	values[7]	34	1			T202	4		T271	18		T320	12
auto[0]	values[5]	values[0]	6	1			T247	6		-	-		-	-
auto[0]	values[5]	values[1]	22	1			T321	22		-	-		-	-
auto[0]	values[5]	values[2]	50	1			T27	14		T203	8		T123	20
auto[0]	values[5]	values[3]	40	1			T30	18		T215	20		T194	2
auto[0]	values[5]	values[4]	54	1			T68	22		T322	2		T323	26
auto[0]	values[5]	values[5]	18	1			T176	8		T324	10		-	-
auto[0]	values[5]	values[6]	28	1			T186	4		T201	2		T115	2
auto[0]	values[5]	values[7]	52	1			T257	12		T230	4		T325	30
auto[0]	values[6]	values[0]	68	1			T106	8		T209	26		T326	22
auto[0]	values[6]	values[1]	70	1			T198	28		T217	22		T327	20
auto[0]	values[6]	values[2]	46	1			T100	6		T28	4		T220	32
auto[0]	values[6]	values[3]	44	1			T117	20		T214	18		T193	6
auto[0]	values[6]	values[4]	28	1			T328	12		T329	6		T330	6
auto[0]	values[6]	values[5]	12	1			T331	4		T332	8		-	-
auto[0]	values[6]	values[7]	68	1			T204	36		T333	32		-	-
auto[0]	values[7]	values[0]	28	1			T225	22		T224	6		-	-
auto[0]	values[7]	values[1]	50	1			T265	18		T334	32		-	-
auto[0]	values[7]	values[2]	44	1			T335	10		T93	26		T246	4
auto[0]	values[7]	values[3]	24	1			T336	24		-	-		-	-
auto[0]	values[7]	values[4]	54	1			T45	16		T29	12		T78	14
auto[0]	values[7]	values[5]	14	1			T8	2		T273	6		T337	6
auto[0]	values[7]	values[6]	50	1			T338	22		T339	24		T206	4
auto[0]	values[7]	values[7]	42	1			T340	10		T248	12		T282	2
auto[1]	values[0]	values[1]	32	1			T76	8		T191	24		-	-
auto[1]	values[0]	values[3]	34	1			T86	32		T341	2		-	-
auto[1]	values[0]	values[4]	24	1			T75	18		T218	6		-	-
auto[1]	values[0]	values[6]	6	1			T245	6		-	-		-	-
auto[1]	values[1]	values[2]	24	1			T231	24		-	-		-	-
auto[1]	values[1]	values[3]	14	1			T80	14		-	-		-	-
auto[1]	values[1]	values[6]	40	1			T5	2		T137	6		T275	32
auto[1]	values[2]	values[1]	18	1			T280	14		T244	4		-	-
auto[1]	values[3]	values[0]	8	1			T342	8		-	-		-	-
auto[1]	values[3]	values[1]	10	1			T70	10		-	-		-	-
auto[1]	values[3]	values[2]	18	1			T229	8		T199	4		T208	6
auto[1]	values[3]	values[4]	2	1			T281	2		-	-		-	-
auto[1]	values[3]	values[5]	72	1			T89	16		T343	18		T344	30
auto[1]	values[4]	values[0]	26	1			T83	26		-	-		-	-
auto[1]	values[4]	values[1]	40	1			T345	18		T205	22		-	-
auto[1]	values[4]	values[2]	20	1			T52	20		-	-		-	-
auto[1]	values[4]	values[3]	50	1			T81	28		T82	22		-	-
auto[1]	values[4]	values[4]	42	1			T346	14		T272	28		-	-
auto[1]	values[5]	values[1]	16	1			T84	16		-	-		-	-
auto[1]	values[5]	values[3]	20	1			T74	20		-	-		-	-
auto[1]	values[5]	values[6]	30	1			T243	30		-	-		-	-
auto[1]	values[6]	values[0]	14	1			T57	14		-	-		-	-
auto[1]	values[6]	values[3]	30	1			T87	30		-	-		-	-
auto[1]	values[6]	values[4]	30	1			T276	30		-	-		-	-
auto[1]	values[6]	values[5]	32	1			T85	22		T216	10		-	-
auto[1]	values[6]	values[6]	2	1			T237	2		-	-		-	-
auto[1]	values[7]	values[0]	18	1			T234	18		-	-		-	-
auto[1]	values[7]	values[1]	2	1			T210	2		-	-		-	-
auto[1]	values[7]	values[2]	6	1			T268	6		-	-		-	-
auto[1]	values[7]	values[3]	18	1			T108	18		-	-		-	-
auto[1]	values[7]	values[4]	14	1			T196	14		-	-		-	-
auto[1]	values[7]	values[5]	30	1			T73	20		T232	8		T347	2