Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.52	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	4	56	93.33

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	4	56	93.33	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	92	1			T2	4		T6	6		T71	2
auto[ReadAddrCrossIntoMailbox]	28	1			T226	2		T269	2		T225	4
auto[ReadAddrCrossOutOfMailbox]	60	1			T6	2		T71	2		T117	6
auto[ReadAddrCrossAllMailbox]	38	1			T6	2		T71	6		T117	10
auto[ReadAddrOutsideMailbox]	712	1			T1	8		T9	4		T5	2

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

465

1

T1

4

T2

2

T9

2

auto[1]

465

1

T1

4

T2

2

T9

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	150	1			T6	8		T31	4		T68	2
read_ops[0x0b]	146	1			T1	6		T9	2		T25	4
read_ops[0x3b]	156	1			T1	2		T2	2		T6	6
read_ops[0x6b]	158	1			T31	2		T52	4		T57	4
read_ops[0xbb]	182	1			T2	2		T9	2		T6	6
read_ops[0xeb]	138	1			T5	2		T6	4		T31	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	4	56	93.33	4

Automatically Generated Cross Bins for cr_all

Element holes

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	NUMBER	STATUS
[read_ops[0x0b]]	[auto[ReadAddrCrossIntoMailbox]]	*	--	--	2
[read_ops[0x3b]]	[auto[ReadAddrCrossAllMailbox]]	*	--	--	2

Covered bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	7	1			T71	1		T117	1		T277	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	7	1			T71	1		T117	1		T277	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	1	1			T312	1		-	-		-	-
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	1	1			T312	1		-	-		-	-
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	5	1			T117	2		T328	1		T302	2
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	5	1			T117	2		T328	1		T302	2
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	2	1			T71	1		T117	1		-	-
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	2	1			T71	1		T117	1		-	-
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	60	1			T6	4		T31	2		T68	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	60	1			T6	4		T31	2		T68	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	5	1			T117	1		T185	1		T200	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	5	1			T117	1		T185	1		T200	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	2	1			T192	1		T340	1		-	-
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	2	1			T192	1		T340	1		-	-
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	4	1			T117	2		T200	1		T340	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	4	1			T117	2		T200	1		T340	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	62	1			T1	3		T9	1		T25	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	62	1			T1	3		T9	1		T25	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	11	1			T2	1		T225	2		T224	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	11	1			T2	1		T225	2		T224	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	3	1			T269	1		T225	1		T306	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	3	1			T269	1		T225	1		T306	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	3	1			T71	1		T269	1		T223	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	3	1			T71	1		T269	1		T223	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	61	1			T1	1		T6	3		T25	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	61	1			T1	1		T6	3		T25	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	6	1			T327	3		T206	1		T312	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	6	1			T327	3		T206	1		T312	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	5	1			T226	1		T328	2		T312	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	5	1			T226	1		T328	2		T312	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	4	1			T117	1		T340	1		T312	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	4	1			T117	1		T340	1		T312	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	3	1			T117	2		T328	1		-	-
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	3	1			T117	2		T328	1		-	-
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	61	1			T31	1		T52	2		T57	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	61	1			T31	1		T52	2		T57	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	9	1			T2	1		T6	3		T235	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	9	1			T2	1		T6	3		T235	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	2	1			T270	1		T223	1		-	-
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	2	1			T270	1		T223	1		-	-
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	11	1			T225	2		T200	2		T233	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	11	1			T225	2		T200	2		T233	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	7	1			T71	1		T302	1		T200	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	7	1			T71	1		T302	1		T200	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	62	1			T9	1		T25	3		T71	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	62	1			T9	1		T25	3		T71	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	8	1			T185	2		T123	3		T223	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	8	1			T185	2		T123	3		T223	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	3	1			T225	1		T320	1		T223	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	3	1			T225	1		T320	1		T223	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	5	1			T6	1		T225	1		T340	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	5	1			T6	1		T225	1		T340	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	3	1			T6	1		T71	1		T306	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	3	1			T6	1		T71	1		T306	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	50	1			T5	1		T31	1		T79	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	50	1			T5	1		T31	1		T79	1