Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	267721	1			T1	1		T2	1		T3	1
all_pins[1]	267721	1			T1	1		T2	1		T3	1
all_pins[2]	267721	1			T1	1		T2	1		T3	1
all_pins[3]	267721	1			T1	1		T2	1		T3	1
all_pins[4]	267721	1			T1	1		T2	1		T3	1
all_pins[5]	267721	1			T1	1		T2	1		T3	1
all_pins[6]	267721	1			T1	1		T2	1		T3	1
all_pins[7]	267721	1			T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2140668	1			T1	8		T2	8		T3	8
values[0x1]	1100	1			T35	22		T42	23		T43	25
transitions[0x0=>0x1]	790	1			T35	16		T42	14		T43	16
transitions[0x1=>0x0]	804	1			T35	16		T42	14		T43	16

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	267583	1			T1	1		T2	1		T3	1
all_pins[0]	values[0x1]	138	1			T35	3		T42	3		T43	5
all_pins[0]	transitions[0x0=>0x1]	93	1			T35	2		T42	2		T43	3
all_pins[0]	transitions[0x1=>0x0]	95	1			T35	2		T42	3		T158	2
all_pins[1]	values[0x0]	267581	1			T1	1		T2	1		T3	1
all_pins[1]	values[0x1]	140	1			T35	3		T42	4		T43	2
all_pins[1]	transitions[0x0=>0x1]	91	1			T35	2		T42	2		T43	2
all_pins[1]	transitions[0x1=>0x0]	91	1			T35	2		T42	2		T43	3
all_pins[2]	values[0x0]	267581	1			T1	1		T2	1		T3	1
all_pins[2]	values[0x1]	140	1			T35	3		T42	4		T43	3
all_pins[2]	transitions[0x0=>0x1]	109	1			T35	2		T42	3		T43	1
all_pins[2]	transitions[0x1=>0x0]	90	1			T43	1		T158	4		T361	2
all_pins[3]	values[0x0]	267600	1			T1	1		T2	1		T3	1
all_pins[3]	values[0x1]	121	1			T35	1		T42	1		T43	3
all_pins[3]	transitions[0x0=>0x1]	79	1			T35	1		T42	1		T43	2
all_pins[3]	transitions[0x1=>0x0]	136	1			T35	1		T42	3		T43	2
all_pins[4]	values[0x0]	267543	1			T1	1		T2	1		T3	1
all_pins[4]	values[0x1]	178	1			T35	1		T42	3		T43	3
all_pins[4]	transitions[0x0=>0x1]	144	1			T35	1		T42	2		T43	2
all_pins[4]	transitions[0x1=>0x0]	83	1			T35	4		T42	1		T43	2
all_pins[5]	values[0x0]	267604	1			T1	1		T2	1		T3	1
all_pins[5]	values[0x1]	117	1			T35	4		T42	2		T43	3
all_pins[5]	transitions[0x0=>0x1]	93	1			T35	2		T43	2		T158	3
all_pins[5]	transitions[0x1=>0x0]	89	1			T35	2		T42	1		T158	4
all_pins[6]	values[0x0]	267608	1			T1	1		T2	1		T3	1
all_pins[6]	values[0x1]	113	1			T35	4		T42	3		T43	1
all_pins[6]	transitions[0x0=>0x1]	79	1			T35	4		T42	2		T43	1
all_pins[6]	transitions[0x1=>0x0]	119	1			T35	3		T42	2		T43	5
all_pins[7]	values[0x0]	267568	1			T1	1		T2	1		T3	1
all_pins[7]	values[0x1]	153	1			T35	3		T42	3		T43	5
all_pins[7]	transitions[0x0=>0x1]	102	1			T35	2		T42	2		T43	3
all_pins[7]	transitions[0x1=>0x0]	101	1			T35	2		T42	2		T43	3