Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	55	73	57.03

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	55	73	57.03	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	254	1			T3	2		T8	2		T70	10
values[1]	316	1			T2	4		T80	14		T185	8
values[2]	394	1			T104	12		T186	4		T91	10
values[3]	454	1			T9	18		T6	24		T68	22
values[4]	372	1			T5	2		T11	20		T45	16
values[5]	268	1			T25	22		T137	6		T187	6
values[6]	446	1			T1	14		T105	4		T29	12
values[7]	518	1			T31	18		T73	20		T188	2

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	448	1			T25	22		T52	20		T29	12
values[1]	380	1			T11	20		T73	20		T46	18
values[2]	312	1			T31	18		T45	16		T77	16
values[3]	550	1			T1	14		T9	18		T6	24
values[4]	256	1			T2	4		T68	22		T70	10
values[5]	350	1			T3	2		T5	2		T189	12
values[6]	438	1			T57	14		T190	2		T187	6
values[7]	288	1			T8	2		T105	4		T184	6

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2986

1

T1

14

T2

4

T3

2

auto[1]

36

1

T52

2

T73

2

T74

2

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	55	73	57.03	55

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[values[0]]	0	1	1
[auto[0]]	[values[5]]	[values[4]]	0	1	1
[auto[1]]	[values[0]]	[values[0] , values[1] , values[2] , values[3] , values[4]]	--	--	5
[auto[1]]	[values[0]]	[values[6] , values[7]]	--	--	2
[auto[1]]	[values[1]]	[values[0] , values[1] , values[2] , values[3]]	--	--	4
[auto[1]]	[values[1]]	[values[5] , values[6] , values[7]]	--	--	3
[auto[1]]	[values[2]]	[values[0] , values[1] , values[2]]	--	--	3
[auto[1]]	[values[2]]	[values[5] , values[6] , values[7]]	--	--	3
[auto[1]]	[values[3]]	[values[1] , values[2] , values[3] , values[4] , values[5]]	--	--	5
[auto[1]]	[values[3]]	[values[7]]	0	1	1
[auto[1]]	[values[4] , values[5] , values[6]]	[values[0] , values[1] , values[2]]	--	--	9
[auto[1]]	[values[4] , values[5] , values[6]]	[values[4] , values[5] , values[6] , values[7]]	--	--	12
[auto[1]]	[values[7]]	[values[0]]	0	1	1
[auto[1]]	[values[7]]	[values[2] , values[3] , values[4]]	--	--	3
[auto[1]]	[values[7]]	[values[6] , values[7]]	--	--	2

Covered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[1]	42	1			T191	24		T192	2		T193	6
auto[0]	values[0]	values[2]	38	1			T77	16		T194	2		T195	20
auto[0]	values[0]	values[3]	16	1			T89	16		-	-		-	-
auto[0]	values[0]	values[4]	42	1			T70	10		T196	14		T197	12
auto[0]	values[0]	values[5]	18	1			T3	2		T85	16		-	-
auto[0]	values[0]	values[6]	54	1			T198	28		T199	4		T200	16
auto[0]	values[0]	values[7]	38	1			T8	2		T184	6		T201	2
auto[0]	values[1]	values[0]	48	1			T202	4		T203	8		T204	36
auto[0]	values[1]	values[1]	44	1			T30	18		T205	22		T206	4
auto[0]	values[1]	values[2]	24	1			T207	18		T208	6		-	-
auto[0]	values[1]	values[3]	82	1			T80	14		T107	26		T209	26
auto[0]	values[1]	values[4]	48	1			T2	4		T210	2		T86	28
auto[0]	values[1]	values[5]	6	1			T211	6		-	-		-	-
auto[0]	values[1]	values[6]	16	1			T212	2		T213	14		-	-
auto[0]	values[1]	values[7]	44	1			T185	8		T124	12		T27	14
auto[0]	values[2]	values[0]	98	1			T214	18		T215	20		T92	10
auto[0]	values[2]	values[1]	10	1			T216	10		-	-		-	-
auto[0]	values[2]	values[2]	22	1			T217	22		-	-		-	-
auto[0]	values[2]	values[3]	112	1			T104	12		T186	4		T81	24
auto[0]	values[2]	values[4]	32	1			T91	10		T218	6		T219	6
auto[0]	values[2]	values[5]	56	1			T220	32		T182	6		T221	4
auto[0]	values[2]	values[6]	52	1			T28	4		T222	24		T223	24
auto[0]	values[2]	values[7]	6	1			T224	6		-	-		-	-
auto[0]	values[3]	values[0]	72	1			T52	18		T56	14		T225	22
auto[0]	values[3]	values[1]	90	1			T226	10		T227	22		T228	8
auto[0]	values[3]	values[2]	10	1			T229	8		T115	2		-	-
auto[0]	values[3]	values[3]	80	1			T9	18		T6	24		T47	14
auto[0]	values[3]	values[4]	38	1			T68	22		T71	16		-	-
auto[0]	values[3]	values[5]	4	1			T230	4		-	-		-	-
auto[0]	values[3]	values[6]	106	1			T57	14		T231	24		T232	8
auto[0]	values[3]	values[7]	50	1			T26	16		T176	8		T233	4
auto[0]	values[4]	values[0]	20	1			T183	2		T234	18		-	-
auto[0]	values[4]	values[1]	80	1			T11	20		T46	18		T78	14
auto[0]	values[4]	values[2]	92	1			T45	16		T235	10		T100	6
auto[0]	values[4]	values[3]	24	1			T236	10		T84	14		-	-
auto[0]	values[4]	values[4]	36	1			T122	12		T237	2		T238	16
auto[0]	values[4]	values[5]	62	1			T5	2		T239	26		T240	34
auto[0]	values[4]	values[6]	4	1			T103	4		-	-		-	-
auto[0]	values[4]	values[7]	52	1			T241	2		T242	20		T243	30
auto[0]	values[5]	values[0]	72	1			T25	22		T137	6		T244	4
auto[0]	values[5]	values[1]	10	1			T245	6		T246	4		-	-
auto[0]	values[5]	values[2]	6	1			T247	6		-	-		-	-
auto[0]	values[5]	values[3]	78	1			T121	16		T83	24		T248	12
auto[0]	values[5]	values[5]	8	1			T174	2		T249	2		T250	4
auto[0]	values[5]	values[6]	84	1			T187	6		T79	28		T123	20
auto[0]	values[5]	values[7]	8	1			T251	8		-	-		-	-
auto[0]	values[6]	values[0]	40	1			T29	12		T252	2		T253	18
auto[0]	values[6]	values[1]	56	1			T254	28		T255	8		T256	4
auto[0]	values[6]	values[2]	56	1			T257	12		T258	14		T259	26
auto[0]	values[6]	values[3]	76	1			T1	14		T76	8		T260	2
auto[0]	values[6]	values[4]	24	1			T106	8		T261	16		-	-
auto[0]	values[6]	values[5]	28	1			T262	20		T263	2		T264	6
auto[0]	values[6]	values[6]	88	1			T190	2		T75	18		T265	18
auto[0]	values[6]	values[7]	70	1			T105	4		T117	20		T108	18
auto[0]	values[7]	values[0]	96	1			T266	18		T267	22		T268	6
auto[0]	values[7]	values[1]	46	1			T73	18		T269	4		T270	24
auto[0]	values[7]	values[2]	64	1			T31	18		T271	18		T272	28
auto[0]	values[7]	values[3]	66	1			T273	6		T274	6		T275	32
auto[0]	values[7]	values[4]	30	1			T276	30		-	-		-	-
auto[0]	values[7]	values[5]	160	1			T189	12		T74	18		T277	2
auto[0]	values[7]	values[6]	32	1			T188	2		T278	26		T279	4
auto[0]	values[7]	values[7]	20	1			T280	14		T281	2		T282	2
auto[1]	values[0]	values[5]	6	1			T85	6		-	-		-	-
auto[1]	values[1]	values[4]	4	1			T86	4		-	-		-	-
auto[1]	values[2]	values[3]	4	1			T81	4		-	-		-	-
auto[1]	values[2]	values[4]	2	1			T283	2		-	-		-	-
auto[1]	values[3]	values[0]	2	1			T52	2		-	-		-	-
auto[1]	values[3]	values[6]	2	1			T82	2		-	-		-	-
auto[1]	values[4]	values[3]	2	1			T84	2		-	-		-	-
auto[1]	values[5]	values[3]	2	1			T83	2		-	-		-	-
auto[1]	values[6]	values[3]	8	1			T87	8		-	-		-	-
auto[1]	values[7]	values[1]	2	1			T73	2		-	-		-	-
auto[1]	values[7]	values[5]	2	1			T74	2		-	-		-	-