Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1340

1

T12

5

T18

6

T20

29

auto[1]

1401

1

T12

9

T18

2

T20

27

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

711

1

T17

4

T61

16

T62

4

auto[1]

2030

1

T12

14

T18

8

T20

56

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2491

1

T12

14

T18

8

T20

56

auto[1]

250

1

T17

3

T61

11

T62

4

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	547	1			T12	2		T18	1		T20	9
valid[1]	589	1			T12	3		T18	4		T20	15
valid[2]	558	1			T12	3		T18	2		T20	8
valid[3]	551	1			T12	3		T20	14		T59	3
valid[4]	496	1			T12	3		T18	1		T20	10

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	49	1			T64	1		T65	2		T67	3
auto[0]	auto[0]	valid[0]	auto[1]	194	1			T12	1		T18	1		T20	4
auto[0]	auto[0]	valid[1]	auto[0]	51	1			T61	2		T64	1		T65	1
auto[0]	auto[0]	valid[1]	auto[1]	208	1			T12	2		T18	3		T20	8
auto[0]	auto[0]	valid[2]	auto[0]	57	1			T17	1		T61	1		T64	3
auto[0]	auto[0]	valid[2]	auto[1]	182	1			T12	1		T18	1		T20	6
auto[0]	auto[0]	valid[3]	auto[0]	39	1			T64	3		T65	1		T72	1
auto[0]	auto[0]	valid[3]	auto[1]	204	1			T20	4		T59	2		T51	13
auto[0]	auto[0]	valid[4]	auto[0]	38	1			T64	5		T67	1		T376	2
auto[0]	auto[0]	valid[4]	auto[1]	188	1			T12	1		T18	1		T20	7
auto[0]	auto[1]	valid[0]	auto[0]	43	1			T64	3		T65	1		T67	2
auto[0]	auto[1]	valid[0]	auto[1]	206	1			T12	1		T20	5		T59	4
auto[0]	auto[1]	valid[1]	auto[0]	45	1			T64	3		T67	3		T375	5
auto[0]	auto[1]	valid[1]	auto[1]	222	1			T12	1		T18	1		T20	7
auto[0]	auto[1]	valid[2]	auto[0]	43	1			T61	1		T64	3		T65	1
auto[0]	auto[1]	valid[2]	auto[1]	228	1			T12	2		T18	1		T20	2
auto[0]	auto[1]	valid[3]	auto[0]	53	1			T64	2		T67	2		T375	5
auto[0]	auto[1]	valid[3]	auto[1]	213	1			T12	3		T20	10		T59	1
auto[0]	auto[1]	valid[4]	auto[0]	43	1			T61	1		T64	1		T67	1
auto[0]	auto[1]	valid[4]	auto[1]	185	1			T12	2		T20	3		T24	2
auto[1]	auto[0]	valid[0]	auto[0]	25	1			T64	1		T65	1		T67	2
auto[1]	auto[0]	valid[1]	auto[0]	34	1			T375	1		T389	1		T377	1
auto[1]	auto[0]	valid[2]	auto[0]	25	1			T375	1		T390	1		T397	2
auto[1]	auto[0]	valid[3]	auto[0]	25	1			T61	1		T64	2		T67	1
auto[1]	auto[0]	valid[4]	auto[0]	21	1			T61	3		T62	2		T67	2
auto[1]	auto[1]	valid[0]	auto[0]	30	1			T17	2		T61	1		T64	1
auto[1]	auto[1]	valid[1]	auto[0]	29	1			T61	5		T64	1		T375	2
auto[1]	auto[1]	valid[2]	auto[0]	23	1			T62	1		T375	2		T389	1
auto[1]	auto[1]	valid[3]	auto[0]	17	1			T17	1		T62	1		T64	2
auto[1]	auto[1]	valid[4]	auto[0]	21	1			T61	1		T64	1		T67	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal