Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17661

1

T15

16

T16

14

T17

162

auto[1]

20106

1

T12

275

T18

8

T20

602

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31469

1

T12

275

T18

8

T15

5

auto[1]

6298

1

T15

11

T16

10

T17

52

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	19542	1			T12	146		T18	8		T15	6
others[1]	3171	1			T12	26		T15	1		T20	43
others[2]	3262	1			T12	21		T15	4		T16	2
others[3]	3575	1			T12	30		T15	1		T20	59
interest[1]	1991	1			T12	10		T16	2		T20	42
interest[4]	12813	1			T12	97		T18	8		T15	4
interest[64]	6226	1			T12	42		T15	4		T16	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	5789	1			T15	4		T16	3		T17	50
auto[0]	auto[0]	others[1]	972	1			T15	1		T17	11		T61	23
auto[0]	auto[0]	others[2]	1005	1			T17	10		T61	21		T62	8
auto[0]	auto[0]	others[3]	1117	1			T17	11		T61	19		T63	2
auto[0]	auto[0]	interest[1]	588	1			T17	5		T61	17		T62	3
auto[0]	auto[0]	interest[4]	3822	1			T15	2		T16	2		T17	32
auto[0]	auto[0]	interest[64]	1892	1			T16	1		T17	23		T61	47
auto[0]	auto[1]	others[0]	10519	1			T12	146		T18	8		T20	312
auto[0]	auto[1]	others[1]	1681	1			T12	26		T20	43		T51	51
auto[0]	auto[1]	others[2]	1726	1			T12	21		T20	48		T51	61
auto[0]	auto[1]	others[3]	1864	1			T12	30		T20	59		T51	59
auto[0]	auto[1]	interest[1]	1049	1			T12	10		T20	42		T51	38
auto[0]	auto[1]	interest[4]	6898	1			T12	97		T18	8		T20	201
auto[0]	auto[1]	interest[64]	3267	1			T12	42		T20	98		T51	96
auto[1]	auto[0]	others[0]	3234	1			T15	2		T16	5		T17	26
auto[1]	auto[0]	others[1]	518	1			T17	3		T61	17		T62	4
auto[1]	auto[0]	others[2]	531	1			T15	4		T16	2		T17	5
auto[1]	auto[0]	others[3]	594	1			T15	1		T17	4		T61	14
auto[1]	auto[0]	interest[1]	354	1			T16	2		T17	2		T61	9
auto[1]	auto[0]	interest[4]	2093	1			T15	2		T16	4		T17	16
auto[1]	auto[0]	interest[64]	1067	1			T15	4		T16	1		T17	12

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal