Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	537	1			T35	10		T42	7		T43	10
all_values[1]	537	1			T35	10		T42	7		T43	10
all_values[2]	537	1			T35	10		T42	7		T43	10
all_values[3]	537	1			T35	10		T42	7		T43	10
all_values[4]	537	1			T35	10		T42	7		T43	10
all_values[5]	537	1			T35	10		T42	7		T43	10
all_values[6]	537	1			T35	10		T42	7		T43	10
all_values[7]	537	1			T35	10		T42	7		T43	10

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2253

1

T35

36

T42

28

T43

34

auto[1]

2043

1

T35

44

T42

28

T43

46

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1675

1

T35

29

T42

15

T43

33

auto[1]

2621

1

T35

51

T42

41

T43

47

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2451

1

T35

44

T42

29

T43

47

auto[1]

1845

1

T35

36

T42

27

T43

33

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	100	1			T42	3		T43	1		T158	8
all_values[0]	auto[0]	auto[0]	auto[1]	60	1			T35	2		T158	3		T361	1
all_values[0]	auto[0]	auto[1]	auto[0]	85	1			T35	1		T43	1		T158	2
all_values[0]	auto[0]	auto[1]	auto[1]	56	1			T35	2		T42	2		T43	1
all_values[0]	auto[1]	auto[0]	auto[1]	127	1			T35	1		T43	2		T158	4
all_values[0]	auto[1]	auto[1]	auto[1]	109	1			T35	4		T42	2		T43	5
all_values[1]	auto[0]	auto[0]	auto[0]	109	1			T35	4		T43	4		T158	4
all_values[1]	auto[0]	auto[0]	auto[1]	52	1			T35	1		T42	2		T43	1
all_values[1]	auto[0]	auto[1]	auto[0]	75	1			T35	2		T158	3		T361	1
all_values[1]	auto[0]	auto[1]	auto[1]	62	1			T35	1		T42	1		T43	1
all_values[1]	auto[1]	auto[0]	auto[1]	132	1			T35	1		T42	1		T43	1
all_values[1]	auto[1]	auto[1]	auto[1]	107	1			T35	1		T42	3		T43	3
all_values[2]	auto[0]	auto[0]	auto[0]	109	1			T35	1		T43	1		T158	8
all_values[2]	auto[0]	auto[0]	auto[1]	39	1			T158	1		T361	2		T362	1
all_values[2]	auto[0]	auto[1]	auto[0]	95	1			T35	1		T42	1		T43	3
all_values[2]	auto[0]	auto[1]	auto[1]	61	1			T35	1		T42	1		T158	1
all_values[2]	auto[1]	auto[0]	auto[1]	119	1			T35	3		T42	1		T43	2
all_values[2]	auto[1]	auto[1]	auto[1]	114	1			T35	4		T42	4		T43	4
all_values[3]	auto[0]	auto[0]	auto[0]	104	1			T35	5		T42	1		T43	2
all_values[3]	auto[0]	auto[0]	auto[1]	70	1			T42	2		T43	4		T158	3
all_values[3]	auto[0]	auto[1]	auto[0]	80	1			T42	1		T43	1		T158	3
all_values[3]	auto[0]	auto[1]	auto[1]	46	1			T35	2		T158	1		T361	1
all_values[3]	auto[1]	auto[0]	auto[1]	129	1			T35	3		T42	2		T43	1
all_values[3]	auto[1]	auto[1]	auto[1]	108	1			T42	1		T43	2		T158	4
all_values[4]	auto[0]	auto[0]	auto[0]	86	1			T35	1		T43	3		T361	5
all_values[4]	auto[0]	auto[0]	auto[1]	37	1			T35	2		T42	1		T43	1
all_values[4]	auto[0]	auto[1]	auto[0]	93	1			T35	3		T43	1		T158	1
all_values[4]	auto[0]	auto[1]	auto[1]	76	1			T42	2		T43	1		T158	3
all_values[4]	auto[1]	auto[0]	auto[1]	120	1			T35	1		T42	4		T158	5
all_values[4]	auto[1]	auto[1]	auto[1]	125	1			T35	3		T43	4		T158	8
all_values[5]	auto[0]	auto[0]	auto[0]	170	1			T35	4		T42	1		T43	2
all_values[5]	auto[0]	auto[1]	auto[0]	149	1			T35	1		T42	2		T43	4
all_values[5]	auto[1]	auto[0]	auto[1]	111	1			T35	1		T42	4		T43	1
all_values[5]	auto[1]	auto[1]	auto[1]	107	1			T35	4		T43	3		T158	3
all_values[6]	auto[0]	auto[0]	auto[0]	128	1			T35	1		T42	3		T43	4
all_values[6]	auto[0]	auto[0]	auto[1]	54	1			T35	1		T158	1		T361	1
all_values[6]	auto[0]	auto[1]	auto[0]	106	1			T35	3		T43	4		T158	4
all_values[6]	auto[0]	auto[1]	auto[1]	46	1			T35	1		T42	1		T158	2
all_values[6]	auto[1]	auto[0]	auto[1]	117	1			T35	1		T42	2		T158	1
all_values[6]	auto[1]	auto[1]	auto[1]	86	1			T35	3		T42	1		T43	2
all_values[7]	auto[0]	auto[0]	auto[0]	114	1			T42	1		T43	1		T158	1
all_values[7]	auto[0]	auto[0]	auto[1]	55	1			T35	1		T43	1		T158	3
all_values[7]	auto[0]	auto[1]	auto[0]	72	1			T35	2		T42	2		T43	1
all_values[7]	auto[0]	auto[1]	auto[1]	62	1			T35	1		T42	2		T43	4
all_values[7]	auto[1]	auto[0]	auto[1]	111	1			T35	2		T43	2		T158	6
all_values[7]	auto[1]	auto[1]	auto[1]	123	1			T35	4		T42	2		T43	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal