Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	250338	1			T1	1		T2	19		T3	1
all_values[1]	250338	1			T1	1		T2	19		T3	1
all_values[2]	250338	1			T1	1		T2	19		T3	1
all_values[3]	250338	1			T1	1		T2	19		T3	1
all_values[4]	250338	1			T1	1		T2	19		T3	1
all_values[5]	250338	1			T1	1		T2	19		T3	1
all_values[6]	250338	1			T1	1		T2	19		T3	1
all_values[7]	250338	1			T1	1		T2	19		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2000407

1

T1

8

T2

152

T3

8

auto[1]

2297

1

T33

32

T24

55

T41

33

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2000493

1

T1

8

T2

150

T3

8

auto[1]

2211

1

T2

2

T15

3

T65

2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	249910	1			T1	1		T2	19		T3	1
all_values[0]	auto[0]	auto[1]	127	1			T33	4		T24	6		T41	3
all_values[0]	auto[1]	auto[0]	169	1			T33	2		T24	7		T41	2
all_values[0]	auto[1]	auto[1]	132	1			T33	6		T24	2		T34	5
all_values[1]	auto[0]	auto[0]	249920	1			T1	1		T2	19		T3	1
all_values[1]	auto[0]	auto[1]	124	1			T33	1		T24	5		T41	4
all_values[1]	auto[1]	auto[0]	180	1			T33	2		T24	4		T41	4
all_values[1]	auto[1]	auto[1]	114	1			T33	2		T34	6		T174	2
all_values[2]	auto[0]	auto[0]	249940	1			T1	1		T2	19		T3	1
all_values[2]	auto[0]	auto[1]	138	1			T33	6		T24	4		T41	4
all_values[2]	auto[1]	auto[0]	146	1			T33	1		T24	4		T41	2
all_values[2]	auto[1]	auto[1]	114	1			T33	1		T24	6		T34	8
all_values[3]	auto[0]	auto[0]	249906	1			T1	1		T2	19		T3	1
all_values[3]	auto[0]	auto[1]	133	1			T33	5		T24	4		T41	2
all_values[3]	auto[1]	auto[0]	181	1			T24	6		T41	6		T34	4
all_values[3]	auto[1]	auto[1]	118	1			T33	1		T34	10		T174	5
all_values[4]	auto[0]	auto[0]	249901	1			T1	1		T2	19		T3	1
all_values[4]	auto[0]	auto[1]	141	1			T85	3		T33	1		T24	4
all_values[4]	auto[1]	auto[0]	163	1			T33	2		T24	4		T41	4
all_values[4]	auto[1]	auto[1]	133	1			T33	4		T24	2		T41	1
all_values[5]	auto[0]	auto[0]	249706	1			T1	1		T2	17		T3	1
all_values[5]	auto[0]	auto[1]	319	1			T2	2		T15	3		T65	2
all_values[5]	auto[1]	auto[0]	200	1			T33	2		T24	5		T41	4
all_values[5]	auto[1]	auto[1]	113	1			T33	1		T24	3		T41	3
all_values[6]	auto[0]	auto[0]	249920	1			T1	1		T2	19		T3	1
all_values[6]	auto[0]	auto[1]	136	1			T33	3		T24	3		T41	2
all_values[6]	auto[1]	auto[0]	165	1			T33	5		T24	4		T41	3
all_values[6]	auto[1]	auto[1]	117	1			T24	1		T34	6		T174	9
all_values[7]	auto[0]	auto[0]	249951	1			T1	1		T2	19		T3	1
all_values[7]	auto[0]	auto[1]	135	1			T33	4		T24	3		T41	1
all_values[7]	auto[1]	auto[0]	135	1			T33	2		T24	3		T41	1
all_values[7]	auto[1]	auto[1]	117	1			T33	1		T24	4		T41	3