Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
78.69	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	1	37	97.37
Crosses	84	25	59	70.24

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	1	1	50.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	23	25	52.08	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	1078	1			T5	12		T6	6		T10	2
auto[SpiFlashAddrCfg]	875	1			T6	2		T12	4		T13	2
auto[SpiFlashAddr3b]	970	1			T4	8		T5	6		T6	10
auto[SpiFlashAddr4b]	872	1			T5	6		T7	6		T8	2

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2848

1

T4

8

T6

18

T7

6

auto[1]

947

1

T5

24

T11

12

T69

16

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1992

1

T4

2

T5

14

T6

10

auto[1]

1803

1

T4

6

T5

10

T6

8

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1524	1			T4	2		T5	12		T6	10
values[1]	76	1			T43	2		T124	4		T93	4
values[2]	153	1			T5	6		T8	2		T67	6
values[3]	198	1			T19	4		T230	6		T72	4
values[4]	200	1			T12	9		T44	4		T124	8
values[5]	151	1			T19	3		T43	2		T188	2
values[6]	150	1			T8	2		T43	2		T85	9
values[7]	192	1			T12	4		T87	2		T67	2
values[8]	1151	1			T4	6		T5	6		T6	8

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3094

1

T4

8

T5

24

T6

18

auto[1]

701

1

T12

13

T19

18

T84

4

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

3671

1

T4

8

T5

22

T6

16

write

124

1

T5

2

T6

2

T67

4

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

1783

1

T4

6

T5

10

T6

10

valids[0x1]

2012

1

T4

2

T5

14

T6

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	166	1			T5	2		T11	2		T95	4
internal_process_ops[0x5a]	203	1			T8	2		T11	2		T95	4
internal_process_ops[0x05]	191	1			T5	4		T8	2		T95	2
internal_process_ops[0x35]	230	1			T6	4		T95	8		T67	8
internal_process_ops[0x15]	166	1			T44	4		T67	6		T187	4
internal_process_ops[0x03]	272	1			T5	4		T12	5		T19	4
internal_process_ops[0x0b]	257	1			T19	4		T84	4		T67	2
internal_process_ops[0x3b]	267	1			T5	2		T11	2		T19	7
internal_process_ops[0x6b]	284	1			T6	6		T7	6		T12	4
internal_process_ops[0xbb]	251	1			T6	2		T12	4		T87	2
internal_process_ops[0xeb]	255	1			T5	4		T8	2		T67	4

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3747

1

T4

8

T5

22

T6

18

auto[1]

48

1

T5

2

T70

2

T71

2

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_upload

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3795

1

T4

8

T5

24

T6

18

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	23	25	52.08	23
Automatically Generated Cross Bins	48	23	25	52.08	23
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Element holes

cp_is_flash	cp_is_write	cp_addr_mode	cp_addr_swap_en	cp_payload_swap_en	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[write]	*	[auto[0]]	[auto[1]]	--	--	4
[auto[0]]	[write]	*	[auto[1]]	[auto[0]]	--	--	4
[auto[1]]	[write]	[auto[SpiFlashAddrDisabled]]	*	*	--	--	4
[auto[1]]	[write]	[auto[SpiFlashAddrCfg]]	[auto[0]]	*	--	--	2
[auto[1]]	[write]	[auto[SpiFlashAddr3b]]	[auto[1]]	*	--	--	2
[auto[1]]	[write]	[auto[SpiFlashAddr4b]]	*	*	--	--	4

Uncovered bins

cp_is_flash	cp_is_write	cp_addr_mode	cp_addr_swap_en	cp_payload_swap_en	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[read]	[auto[SpiFlashAddr4b]]	[auto[1]]	[auto[0]]	0	1	1
[auto[1]]	[write]	[auto[SpiFlashAddrCfg]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[write]	[auto[SpiFlashAddr3b]]	[auto[0]]	[auto[0]]	0	1	1

Covered bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

820

1

T6

6

T10

2

T8

2

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

224

1

T5

12

T11

6

T69

4

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

394

1

T6

2

T13

2

T87

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

218

1

T69

6

T197

2

T70

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

492

1

T4

8

T6

8

T8

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

260

1

T5

6

T11

4

T69

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

382

1

T7

6

T8

2

T43

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

186

1

T5

4

T11

2

T69

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10

1

T196

2

T306

2

T214

6

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

8

1

T76

2

T80

4

T299

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

22

1

T194

4

T217

2

T341

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

16

1

T76

2

T78

2

T79

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

14

1

T6

2

T237

2

T311

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

8

1

T70

2

T76

4

T298

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

26

1

T67

4

T68

2

T255

8

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

14

1

T5

2

T71

2

T75

4

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

14

1

T24

9

T102

5

-

-

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

2

1

T24

1

T102

1

-

-

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

216

1

T12

4

T19

4

T124

4

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

5

1

T102

5

-

-

-

-

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

192

1

T12

4

T19

4

T85

9

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2

1

T24

2

-

-

-

-

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

264

1

T12

5

T19

10

T84

4

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

4

1

T102

4

-

-

-

-

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

2

1

T102

2

-

-

-

-

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	286	1			T5	4		T6	2		T10	2
auto[0]	values[0]	valids[0x1]	1124	1			T4	2		T5	8		T6	8
auto[0]	values[1]	valids[0x1]	72	1			T43	2		T93	4		T91	2
auto[0]	values[2]	valids[0x0]	60	1			T5	2		T8	2		T67	4
auto[0]	values[2]	valids[0x1]	38	1			T5	4		T67	2		T188	4
auto[0]	values[3]	valids[0x0]	104	1			T230	2		T72	4		T198	2
auto[0]	values[3]	valids[0x1]	42	1			T230	4		T68	2		T113	2
auto[0]	values[4]	valids[0x0]	102	1			T45	6		T230	2		T242	4
auto[0]	values[4]	valids[0x1]	48	1			T44	4		T112	6		T257	4
auto[0]	values[5]	valids[0x0]	80	1			T43	2		T188	2		T272	2
auto[0]	values[5]	valids[0x1]	38	1			T70	2		T73	2		T206	2
auto[0]	values[6]	valids[0x0]	44	1			T46	2		T89	2		T73	2
auto[0]	values[6]	valids[0x1]	44	1			T8	2		T43	2		T230	2
auto[0]	values[7]	valids[0x0]	82	1			T87	2		T67	2		T69	2
auto[0]	values[7]	valids[0x1]	44	1			T191	6		T92	4		T219	8
auto[0]	values[8]	valids[0x0]	596	1			T4	6		T5	4		T6	8
auto[0]	values[8]	valids[0x1]	290	1			T5	2		T11	6		T74	4
auto[1]	values[0]	valids[0x0]	14	1			T24	4		T342	5		T102	5
auto[1]	values[0]	valids[0x1]	100	1			T84	4		T86	9		T24	7
auto[1]	values[1]	valids[0x1]	4	1			T124	4		-	-		-	-
auto[1]	values[2]	valids[0x0]	46	1			T85	7		T343	4		T344	3
auto[1]	values[2]	valids[0x1]	9	1			T345	4		T346	2		T347	1
auto[1]	values[3]	valids[0x0]	36	1			T166	2		T344	5		T348	5
auto[1]	values[3]	valids[0x1]	16	1			T19	4		T345	4		T343	5
auto[1]	values[4]	valids[0x0]	37	1			T12	4		T85	3		T349	2
auto[1]	values[4]	valids[0x1]	13	1			T12	5		T124	8		-	-
auto[1]	values[5]	valids[0x0]	16	1			T19	3		T24	1		T350	4
auto[1]	values[5]	valids[0x1]	17	1			T24	1		T349	5		T351	3
auto[1]	values[6]	valids[0x0]	30	1			T352	8		T353	4		T354	3
auto[1]	values[6]	valids[0x1]	32	1			T85	9		T352	4		T60	12
auto[1]	values[7]	valids[0x0]	52	1			T12	4		T86	3		T349	4
auto[1]	values[7]	valids[0x1]	14	1			T349	5		T355	5		T356	4
auto[1]	values[8]	valids[0x0]	198	1			T19	7		T124	5		T86	3
auto[1]	values[8]	valids[0x1]	67	1			T19	4		T24	4		T357	4