Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg
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Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
36.36 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv


Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 16 2 14 87.50
Crosses 72 54 18 25.00


Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_busy_bit 2 1 1 50.00 100 1 1 2
cp_is_host_read 2 0 2 100.00 100 1 1 2
cp_other_status 8 0 8 100.00 100 1 1 8
cp_sw_read_while_csb_active 2 0 2 100.00 100 1 1 2
cp_wel_bit 2 1 1 50.00 100 1 1 2


Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all_except_csb 64 48 16 25.00 100 1 1 0
cr_busyXwelXcsb 8 6 2 25.00 100 1 1 0


Summary for Variable cp_busy_bit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_busy_bit

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1715992 1 T4 1 T9 1 T5 1


Summary for Variable cp_is_host_read

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_is_host_read

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1586084 1 T4 1 T9 1 T5 1
auto[1] 129908 1 T43 16 T44 16224 T45 1186


Summary for Variable cp_other_status

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 8 0 8 100.00


Automatically Generated Bins for cp_other_status

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:524287] 385695 1 T4 1 T9 1 T5 1
auto[524288:1048575] 208336 1 T7 815 T10 1949 T8 2
auto[1048576:1572863] 152195 1 T7 476 T10 1 T8 9
auto[1572864:2097151] 173272 1 T7 664 T12 25 T95 475
auto[2097152:2621439] 243256 1 T7 356 T10 1 T12 1779
auto[2621440:3145727] 134614 1 T7 176 T10 1225 T8 62
auto[3145728:3670015] 224347 1 T7 337 T10 1645 T8 70
auto[3670016:4194303] 194277 1 T7 242 T8 1 T12 778


Summary for Variable cp_sw_read_while_csb_active

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_sw_read_while_csb_active

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 142533 1 T4 1 T9 1 T5 1
auto[1] 1573459 1 T7 3077 T10 5095 T8 248


Summary for Variable cp_wel_bit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_wel_bit

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1715992 1 T4 1 T9 1 T5 1


Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 48 16 25.00 48


Automatically Generated Cross Bins for cr_all_except_csb

Element holes
cp_busy_bitcp_wel_bitcp_other_statuscp_is_host_readCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[1]] * * -- -- 16
[auto[1]] * * * -- -- 32


Covered bins
cp_busy_bitcp_wel_bitcp_other_statuscp_is_host_readCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0:524287] auto[0] 294025 1 T4 1 T9 1 T5 1
auto[0] auto[0] auto[0:524287] auto[1] 91670 1 T43 16 T44 3966 T45 144
auto[0] auto[0] auto[524288:1048575] auto[0] 203885 1 T7 815 T10 1949 T8 2
auto[0] auto[0] auto[524288:1048575] auto[1] 4451 1 T44 2689 T45 27 T185 257
auto[0] auto[0] auto[1048576:1572863] auto[0] 146871 1 T7 476 T10 1 T8 9
auto[0] auto[0] auto[1048576:1572863] auto[1] 5324 1 T185 4211 T119 6 T112 5
auto[0] auto[0] auto[1572864:2097151] auto[0] 169024 1 T7 664 T12 25 T95 475
auto[0] auto[0] auto[1572864:2097151] auto[1] 4248 1 T45 119 T185 2611 T186 6
auto[0] auto[0] auto[2097152:2621439] auto[0] 224970 1 T7 356 T10 1 T12 1779
auto[0] auto[0] auto[2097152:2621439] auto[1] 18286 1 T44 7790 T45 471 T119 1
auto[0] auto[0] auto[2621440:3145727] auto[0] 132303 1 T7 176 T10 1225 T8 62
auto[0] auto[0] auto[2621440:3145727] auto[1] 2311 1 T45 224 T119 1 T186 123
auto[0] auto[0] auto[3145728:3670015] auto[0] 223422 1 T7 337 T10 1645 T8 70
auto[0] auto[0] auto[3145728:3670015] auto[1] 925 1 T185 70 T119 211 T112 12
auto[0] auto[0] auto[3670016:4194303] auto[0] 191584 1 T7 242 T8 1 T12 778
auto[0] auto[0] auto[3670016:4194303] auto[1] 2693 1 T44 1779 T45 201 T119 4


Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 6 2 25.00 6


Automatically Generated Cross Bins for cr_busyXwelXcsb

Element holes
cp_busy_bitcp_wel_bitcp_sw_read_while_csb_activeCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[1]] * -- -- 2
[auto[1]] * * -- -- 4


Covered bins
cp_busy_bitcp_wel_bitcp_sw_read_while_csb_activeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] 142533 1 T4 1 T9 1 T5 1
auto[0] auto[0] auto[1] 1573459 1 T7 3077 T10 5095 T8 248

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