Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
77.40	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	33	95	74.22

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	33	95	74.22	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2160

1

T4

8

T6

18

T7

6

auto[1]

934

1

T5

24

T11

12

T69

16

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	312	1			T5	24		T7	6		T91	8
values[1]	480	1			T95	18		T43	10		T98	2
values[2]	406	1			T4	8		T10	2		T29	4
values[3]	472	1			T87	2		T67	30		T72	18
values[4]	490	1			T6	18		T69	16		T96	18
values[5]	380	1			T8	6		T44	12		T47	18
values[6]	294	1			T187	6		T191	22		T190	2
values[7]	260	1			T11	12		T13	2		T93	16

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	346	1			T93	16		T28	4		T184	6
values[1]	380	1			T5	24		T6	18		T8	6
values[2]	470	1			T10	2		T191	22		T27	4
values[3]	310	1			T13	2		T29	4		T96	18
values[4]	556	1			T7	6		T43	10		T67	30
values[5]	430	1			T4	8		T11	12		T87	2
values[6]	236	1			T95	18		T72	18		T217	22
values[7]	366	1			T242	6		T185	8		T68	26

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	33	95	74.22	33

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[2]]	[values[0]]	0	1	1
[auto[0]]	[values[5]]	[values[2]]	0	1	1
[auto[0]]	[values[5]]	[values[7]]	0	1	1
[auto[0]]	[values[6]]	[values[5]]	0	1	1
[auto[1]]	[values[0]]	[values[0]]	0	1	1
[auto[1]]	[values[0]]	[values[5] , values[6] , values[7]]	--	--	3
[auto[1]]	[values[1]]	[values[0]]	0	1	1
[auto[1]]	[values[1]]	[values[3]]	0	1	1
[auto[1]]	[values[2]]	[values[4] , values[5] , values[6] , values[7]]	--	--	4
[auto[1]]	[values[3]]	[values[1]]	0	1	1
[auto[1]]	[values[3]]	[values[4]]	0	1	1
[auto[1]]	[values[3]]	[values[6] , values[7]]	--	--	2
[auto[1]]	[values[4]]	[values[2] , values[3]]	--	--	2
[auto[1]]	[values[4]]	[values[5]]	0	1	1
[auto[1]]	[values[5]]	[values[0] , values[1]]	--	--	2
[auto[1]]	[values[5]]	[values[5] , values[6] , values[7]]	--	--	3
[auto[1]]	[values[6]]	[values[2] , values[3]]	--	--	2
[auto[1]]	[values[6]]	[values[5]]	0	1	1
[auto[1]]	[values[6]]	[values[7]]	0	1	1
[auto[1]]	[values[7]]	[values[3] , values[4]]	--	--	2
[auto[1]]	[values[7]]	[values[6]]	0	1	1

Covered bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	60	1			T90	10		T290	14		T56	8
auto[0]	values[0]	values[1]	36	1			T230	22		T301	2		T302	12
auto[0]	values[0]	values[2]	60	1			T219	30		T251	18		T209	12
auto[0]	values[0]	values[3]	2	1			T303	2		-	-		-	-
auto[0]	values[0]	values[4]	12	1			T7	6		T261	2		T283	4
auto[0]	values[0]	values[5]	32	1			T91	8		T274	24		-	-
auto[0]	values[0]	values[6]	22	1			T217	22		-	-		-	-
auto[0]	values[0]	values[7]	12	1			T196	4		T270	2		T201	6
auto[0]	values[1]	values[0]	36	1			T82	14		T120	12		T304	10
auto[0]	values[1]	values[1]	42	1			T119	14		T207	28		-	-
auto[0]	values[1]	values[2]	80	1			T226	16		T221	14		T208	20
auto[0]	values[1]	values[3]	14	1			T101	8		T202	6		-	-
auto[0]	values[1]	values[4]	72	1			T43	10		T206	6		T218	28
auto[0]	values[1]	values[5]	22	1			T26	2		T280	12		T250	8
auto[0]	values[1]	values[6]	28	1			T95	18		T275	10		-	-
auto[0]	values[1]	values[7]	18	1			T267	6		T305	12		-	-
auto[0]	values[2]	values[1]	34	1			T272	6		T306	12		T307	16
auto[0]	values[2]	values[2]	18	1			T10	2		T27	4		T92	12
auto[0]	values[2]	values[3]	36	1			T29	4		T89	6		T284	26
auto[0]	values[2]	values[4]	60	1			T45	14		T256	28		T199	8
auto[0]	values[2]	values[5]	80	1			T4	8		T74	14		T238	16
auto[0]	values[2]	values[6]	10	1			T293	2		T61	8		-	-
auto[0]	values[2]	values[7]	62	1			T242	6		T185	8		T289	32
auto[0]	values[3]	values[0]	32	1			T184	6		T254	8		T308	8
auto[0]	values[3]	values[1]	58	1			T237	16		T297	30		T309	12
auto[0]	values[3]	values[2]	34	1			T310	18		T253	16		-	-
auto[0]	values[3]	values[3]	28	1			T211	2		T311	16		T312	2
auto[0]	values[3]	values[4]	66	1			T67	30		T236	4		T25	22
auto[0]	values[3]	values[5]	68	1			T87	2		T194	10		T215	20
auto[0]	values[3]	values[6]	54	1			T72	18		T265	20		T99	4
auto[0]	values[3]	values[7]	22	1			T313	10		T314	4		T315	8
auto[0]	values[4]	values[0]	20	1			T316	20		-	-		-	-
auto[0]	values[4]	values[1]	18	1			T6	18		-	-		-	-
auto[0]	values[4]	values[2]	36	1			T192	16		T252	10		T227	10
auto[0]	values[4]	values[3]	78	1			T96	18		T193	14		T188	18
auto[0]	values[4]	values[4]	52	1			T198	2		T195	18		T317	4
auto[0]	values[4]	values[5]	42	1			T113	16		T318	26		-	-
auto[0]	values[4]	values[6]	14	1			T234	10		T319	4		-	-
auto[0]	values[4]	values[7]	52	1			T269	16		T264	18		T320	4
auto[0]	values[5]	values[0]	76	1			T28	4		T263	32		T121	10
auto[0]	values[5]	values[1]	6	1			T8	6		-	-		-	-
auto[0]	values[5]	values[3]	28	1			T321	22		T278	6		-	-
auto[0]	values[5]	values[4]	78	1			T47	18		T186	12		T259	14
auto[0]	values[5]	values[5]	44	1			T44	12		T223	32		-	-
auto[0]	values[5]	values[6]	30	1			T247	12		T322	16		T323	2
auto[0]	values[6]	values[0]	6	1			T279	6		-	-		-	-
auto[0]	values[6]	values[1]	6	1			T187	6		-	-		-	-
auto[0]	values[6]	values[2]	28	1			T191	22		T190	2		T249	4
auto[0]	values[6]	values[3]	8	1			T324	8		-	-		-	-
auto[0]	values[6]	values[4]	64	1			T216	22		T233	24		T325	18
auto[0]	values[6]	values[6]	14	1			T326	2		T248	12		-	-
auto[0]	values[6]	values[7]	104	1			T68	26		T189	2		T112	20
auto[0]	values[7]	values[0]	32	1			T327	2		T54	4		T328	18
auto[0]	values[7]	values[1]	2	1			T329	2		-	-		-	-
auto[0]	values[7]	values[2]	36	1			T330	26		T331	10		-	-
auto[0]	values[7]	values[3]	10	1			T13	2		T57	8		-	-
auto[0]	values[7]	values[4]	20	1			T46	8		T294	8		T245	4
auto[0]	values[7]	values[5]	10	1			T332	10		-	-		-	-
auto[0]	values[7]	values[6]	10	1			T296	10		-	-		-	-
auto[0]	values[7]	values[7]	26	1			T220	26		-	-		-	-
auto[1]	values[0]	values[1]	24	1			T5	24		-	-		-	-
auto[1]	values[0]	values[2]	24	1			T333	24		-	-		-	-
auto[1]	values[0]	values[3]	10	1			T285	8		T334	2		-	-
auto[1]	values[0]	values[4]	18	1			T70	18		-	-		-	-
auto[1]	values[1]	values[1]	62	1			T98	2		T335	30		T336	30
auto[1]	values[1]	values[2]	2	1			T287	2		-	-		-	-
auto[1]	values[1]	values[4]	30	1			T71	8		T258	22		-	-
auto[1]	values[1]	values[5]	56	1			T262	24		T299	32		-	-
auto[1]	values[1]	values[6]	16	1			T228	16		-	-		-	-
auto[1]	values[1]	values[7]	2	1			T225	2		-	-		-	-
auto[1]	values[2]	values[0]	10	1			T300	10		-	-		-	-
auto[1]	values[2]	values[1]	8	1			T197	8		-	-		-	-
auto[1]	values[2]	values[2]	38	1			T239	32		T337	6		-	-
auto[1]	values[2]	values[3]	50	1			T231	14		T204	36		-	-
auto[1]	values[3]	values[0]	24	1			T80	24		-	-		-	-
auto[1]	values[3]	values[2]	22	1			T77	22		-	-		-	-
auto[1]	values[3]	values[3]	8	1			T266	8		-	-		-	-
auto[1]	values[3]	values[5]	56	1			T243	28		T338	28		-	-
auto[1]	values[4]	values[0]	28	1			T83	28		-	-		-	-
auto[1]	values[4]	values[1]	38	1			T78	14		T291	24		-	-
auto[1]	values[4]	values[4]	42	1			T69	16		T76	26		-	-
auto[1]	values[4]	values[6]	26	1			T75	26		-	-		-	-
auto[1]	values[4]	values[7]	44	1			T339	22		T282	22		-	-
auto[1]	values[5]	values[2]	66	1			T73	26		T235	32		T79	8
auto[1]	values[5]	values[3]	38	1			T295	8		T340	30		-	-
auto[1]	values[5]	values[4]	14	1			T81	14		-	-		-	-
auto[1]	values[6]	values[0]	6	1			T298	6		-	-		-	-
auto[1]	values[6]	values[1]	18	1			T246	18		-	-		-	-
auto[1]	values[6]	values[4]	28	1			T224	28		-	-		-	-
auto[1]	values[6]	values[6]	12	1			T292	12		-	-		-	-
auto[1]	values[7]	values[0]	16	1			T93	16		-	-		-	-
auto[1]	values[7]	values[1]	28	1			T200	28		-	-		-	-
auto[1]	values[7]	values[2]	26	1			T257	26		-	-		-	-
auto[1]	values[7]	values[5]	20	1			T11	12		T276	8		-	-
auto[1]	values[7]	values[7]	24	1			T286	24		-	-		-	-