Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.52	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	4	56	93.33

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	4	56	93.33	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	84	1			T45	6		T91	4		T46	4
auto[ReadAddrCrossIntoMailbox]	28	1			T96	2		T193	2		T195	2
auto[ReadAddrCrossOutOfMailbox]	32	1			T96	8		T193	4		T195	2
auto[ReadAddrCrossAllMailbox]	20	1			T96	2		T193	2		T195	4
auto[ReadAddrOutsideMailbox]	726	1			T5	10		T6	8		T8	2

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

445

1

T5

5

T6

4

T8

1

auto[1]

445

1

T5

5

T6

4

T8

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	144	1			T5	4		T98	2		T93	4
read_ops[0x0b]	126	1			T67	2		T69	4		T191	4
read_ops[0x3b]	166	1			T5	2		T11	2		T74	2
read_ops[0x6b]	136	1			T6	6		T230	2		T242	4
read_ops[0xbb]	152	1			T6	2		T87	2		T45	4
read_ops[0xeb]	166	1			T5	4		T8	2		T67	4

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	4	56	93.33	4

Automatically Generated Cross Bins for cr_all

Element holes

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	NUMBER	STATUS
[read_ops[0x3b]]	[auto[ReadAddrCrossAllMailbox]]	*	--	--	2
[read_ops[0x6b]]	[auto[ReadAddrCrossOutOfMailbox]]	*	--	--	2

Covered bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	3	1			T195	1		T301	1		T121	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	3	1			T195	1		T301	1		T121	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	1	1			T256	1		-	-		-	-
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	1	1			T256	1		-	-		-	-
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	5	1			T256	2		T220	1		T320	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	5	1			T256	2		T220	1		T320	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	2	1			T256	2		-	-		-	-
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	2	1			T256	2		-	-		-	-
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	61	1			T5	2		T98	1		T93	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	61	1			T5	2		T98	1		T93	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	6	1			T91	1		T190	1		T195	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	6	1			T91	1		T190	1		T195	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	2	1			T96	1		T195	1		-	-
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	2	1			T96	1		T195	1		-	-
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	2	1			T96	2		-	-		-	-
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	2	1			T96	2		-	-		-	-
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	1	1			T96	1		-	-		-	-
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	1	1			T96	1		-	-		-	-
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	52	1			T67	1		T69	2		T191	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	52	1			T67	1		T69	2		T191	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	9	1			T45	1		T91	1		T193	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	9	1			T45	1		T91	1		T193	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	3	1			T219	1		T82	2		-	-
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	3	1			T219	1		T82	2		-	-
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	3	1			T96	1		T193	1		T219	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	3	1			T96	1		T193	1		T219	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	68	1			T5	1		T11	1		T74	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	68	1			T5	1		T11	1		T74	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	5	1			T244	1		T275	1		T227	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	5	1			T244	1		T275	1		T227	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	2	1			T82	1		T260	1		-	-
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	2	1			T82	1		T260	1		-	-
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	3	1			T195	1		T82	1		T358	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	3	1			T195	1		T82	1		T358	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	58	1			T6	3		T230	1		T242	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	58	1			T6	3		T230	1		T242	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	12	1			T45	2		T46	1		T189	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	12	1			T45	2		T46	1		T189	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	3	1			T219	1		T220	2		-	-
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	3	1			T219	1		T220	2		-	-
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	5	1			T96	1		T195	1		T256	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	5	1			T96	1		T195	1		T256	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	2	1			T195	1		T219	1		-	-
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	2	1			T195	1		T219	1		-	-
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	54	1			T6	1		T87	1		T96	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	54	1			T6	1		T87	1		T96	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	7	1			T46	1		T220	1		T273	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	7	1			T46	1		T220	1		T273	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	3	1			T193	1		T220	2		-	-
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	3	1			T193	1		T220	2		-	-
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	1	1			T193	1		-	-		-	-
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	1	1			T193	1		-	-		-	-
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	2	1			T193	1		T359	1		-	-
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	2	1			T193	1		T359	1		-	-
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	70	1			T5	2		T8	1		T67	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	70	1			T5	2		T8	1		T67	2