Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	250338	1			T1	1		T2	19		T3	1
all_pins[1]	250338	1			T1	1		T2	19		T3	1
all_pins[2]	250338	1			T1	1		T2	19		T3	1
all_pins[3]	250338	1			T1	1		T2	19		T3	1
all_pins[4]	250338	1			T1	1		T2	19		T3	1
all_pins[5]	250338	1			T1	1		T2	19		T3	1
all_pins[6]	250338	1			T1	1		T2	19		T3	1
all_pins[7]	250338	1			T1	1		T2	19		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2001746	1			T1	8		T2	152		T3	8
values[0x1]	958	1			T33	16		T24	18		T41	7
transitions[0x0=>0x1]	731	1			T33	14		T24	17		T41	6
transitions[0x1=>0x0]	741	1			T33	14		T24	17		T41	6

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	250206	1			T1	1		T2	19		T3	1
all_pins[0]	values[0x1]	132	1			T33	6		T24	2		T34	5
all_pins[0]	transitions[0x0=>0x1]	95	1			T33	5		T24	2		T34	2
all_pins[0]	transitions[0x1=>0x0]	77	1			T33	1		T34	3		T174	2
all_pins[1]	values[0x0]	250224	1			T1	1		T2	19		T3	1
all_pins[1]	values[0x1]	114	1			T33	2		T34	6		T174	2
all_pins[1]	transitions[0x0=>0x1]	86	1			T33	2		T34	2		T174	1
all_pins[1]	transitions[0x1=>0x0]	86	1			T33	1		T24	6		T34	4
all_pins[2]	values[0x0]	250224	1			T1	1		T2	19		T3	1
all_pins[2]	values[0x1]	114	1			T33	1		T24	6		T34	8
all_pins[2]	transitions[0x0=>0x1]	87	1			T33	1		T24	6		T34	3
all_pins[2]	transitions[0x1=>0x0]	91	1			T33	1		T34	5		T174	4
all_pins[3]	values[0x0]	250220	1			T1	1		T2	19		T3	1
all_pins[3]	values[0x1]	118	1			T33	1		T34	10		T174	5
all_pins[3]	transitions[0x0=>0x1]	88	1			T33	1		T34	10		T174	2
all_pins[3]	transitions[0x1=>0x0]	103	1			T33	4		T24	2		T41	1
all_pins[4]	values[0x0]	250205	1			T1	1		T2	19		T3	1
all_pins[4]	values[0x1]	133	1			T33	4		T24	2		T41	1
all_pins[4]	transitions[0x0=>0x1]	107	1			T33	4		T24	2		T34	1
all_pins[4]	transitions[0x1=>0x0]	87	1			T33	1		T24	3		T41	2
all_pins[5]	values[0x0]	250225	1			T1	1		T2	19		T3	1
all_pins[5]	values[0x1]	113	1			T33	1		T24	3		T41	3
all_pins[5]	transitions[0x0=>0x1]	91	1			T33	1		T24	3		T41	3
all_pins[5]	transitions[0x1=>0x0]	95	1			T24	1		T34	4		T174	8
all_pins[6]	values[0x0]	250221	1			T1	1		T2	19		T3	1
all_pins[6]	values[0x1]	117	1			T24	1		T34	6		T174	9
all_pins[6]	transitions[0x0=>0x1]	92	1			T24	1		T34	3		T174	8
all_pins[6]	transitions[0x1=>0x0]	92	1			T33	1		T24	4		T41	3
all_pins[7]	values[0x0]	250221	1			T1	1		T2	19		T3	1
all_pins[7]	values[0x1]	117	1			T33	1		T24	4		T41	3
all_pins[7]	transitions[0x0=>0x1]	85	1			T24	3		T41	3		T34	4
all_pins[7]	transitions[0x1=>0x0]	110	1			T33	5		T24	1		T34	4