Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
65.07	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	51	77	60.16

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	51	77	60.16	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	366	1			T4	8		T98	2		T93	16
values[1]	324	1			T13	2		T69	16		T187	6
values[2]	506	1			T10	2		T95	18		T29	4
values[3]	398	1			T6	18		T11	12		T74	14
values[4]	418	1			T67	30		T188	18		T189	2
values[5]	410	1			T87	2		T43	10		T91	8
values[6]	292	1			T8	6		T44	12		T190	2
values[7]	380	1			T5	24		T7	6		T27	4

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	338	1			T5	24		T8	6		T191	22
values[1]	344	1			T46	8		T192	16		T188	18
values[2]	402	1			T7	6		T10	2		T87	2
values[3]	400	1			T4	8		T6	18		T11	12
values[4]	354	1			T193	14		T189	2		T194	10
values[5]	460	1			T29	4		T44	12		T67	30
values[6]	502	1			T95	18		T190	2		T119	14
values[7]	294	1			T195	18		T196	4		T82	14

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3048

1

T4

8

T5

22

T6

18

auto[1]

46

1

T5

2

T70

2

T71

2

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	51	77	60.16	51

Automatically Generated Cross Bins for cr_all

Element holes

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[1]]	*	--	--	8

Uncovered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[3]]	[values[4]]	0	1	1
[auto[0]]	[values[4]]	[values[2]]	0	1	1
[auto[1]]	[values[0]]	[values[0] , values[1] , values[2]]	--	--	3
[auto[1]]	[values[0]]	[values[4] , values[5] , values[6] , values[7]]	--	--	4
[auto[1]]	[values[2]]	[values[1]]	0	1	1
[auto[1]]	[values[2]]	[values[3] , values[4] , values[5] , values[6]]	--	--	4
[auto[1]]	[values[3]]	[values[0] , values[1] , values[2]]	--	--	3
[auto[1]]	[values[3]]	[values[4] , values[5]]	--	--	2
[auto[1]]	[values[3]]	[values[7]]	0	1	1
[auto[1]]	[values[4]]	[values[0]]	0	1	1
[auto[1]]	[values[4]]	[values[2] , values[3]]	--	--	2
[auto[1]]	[values[4]]	[values[5]]	0	1	1
[auto[1]]	[values[5]]	[values[0]]	0	1	1
[auto[1]]	[values[5]]	[values[2] , values[3] , values[4] , values[5] , values[6] , values[7]]	--	--	6
[auto[1]]	[values[6]]	[values[0] , values[1] , values[2]]	--	--	3
[auto[1]]	[values[6]]	[values[4] , values[5] , values[6] , values[7]]	--	--	4
[auto[1]]	[values[7]]	[values[1] , values[2]]	--	--	2
[auto[1]]	[values[7]]	[values[4] , values[5]]	--	--	2
[auto[1]]	[values[7]]	[values[7]]	0	1	1

Covered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	44	1			T197	8		T184	6		T198	2
auto[0]	values[0]	values[1]	52	1			T192	16		T199	8		T200	28
auto[0]	values[0]	values[2]	52	1			T112	20		T201	6		T202	6
auto[0]	values[0]	values[3]	18	1			T4	8		T98	2		T203	4
auto[0]	values[0]	values[4]	74	1			T204	36		T205	10		T121	10
auto[0]	values[0]	values[5]	38	1			T93	16		T89	6		T206	6
auto[0]	values[0]	values[6]	60	1			T207	28		T208	20		T209	12
auto[0]	values[0]	values[7]	26	1			T101	8		T210	18		-	-
auto[0]	values[1]	values[0]	24	1			T191	22		T211	2		-	-
auto[0]	values[1]	values[1]	26	1			T212	2		T213	24		-	-
auto[0]	values[1]	values[2]	64	1			T69	16		T214	28		T215	20
auto[0]	values[1]	values[3]	24	1			T13	2		T216	22		-	-
auto[0]	values[1]	values[4]	76	1			T113	16		T217	22		T218	28
auto[0]	values[1]	values[5]	72	1			T187	6		T219	30		T220	26
auto[0]	values[1]	values[6]	14	1			T221	14		-	-		-	-
auto[0]	values[1]	values[7]	24	1			T82	14		T222	10		-	-
auto[0]	values[2]	values[0]	56	1			T223	32		T224	22		T225	2
auto[0]	values[2]	values[1]	30	1			T226	16		T54	4		T227	10
auto[0]	values[2]	values[2]	56	1			T10	2		T228	16		T229	8
auto[0]	values[2]	values[3]	94	1			T230	22		T28	4		T231	14
auto[0]	values[2]	values[4]	50	1			T232	6		T99	4		T233	24
auto[0]	values[2]	values[5]	88	1			T29	4		T234	10		T235	32
auto[0]	values[2]	values[6]	82	1			T95	18		T236	4		T237	16
auto[0]	values[2]	values[7]	38	1			T195	18		T77	20		-	-
auto[0]	values[3]	values[0]	94	1			T238	16		T25	22		T239	32
auto[0]	values[3]	values[1]	50	1			T186	12		T240	6		T241	22
auto[0]	values[3]	values[2]	34	1			T242	6		T243	28		-	-
auto[0]	values[3]	values[3]	92	1			T6	18		T11	12		T74	14
auto[0]	values[3]	values[5]	78	1			T45	14		T185	8		T90	10
auto[0]	values[3]	values[6]	20	1			T244	2		T245	4		T246	14
auto[0]	values[3]	values[7]	24	1			T247	12		T248	12		-	-
auto[0]	values[4]	values[0]	12	1			T249	4		T250	8		-	-
auto[0]	values[4]	values[1]	76	1			T188	18		T251	18		T76	18
auto[0]	values[4]	values[3]	26	1			T252	10		T253	16		-	-
auto[0]	values[4]	values[4]	16	1			T189	2		T254	8		T79	6
auto[0]	values[4]	values[5]	90	1			T67	30		T255	30		T256	28
auto[0]	values[4]	values[6]	146	1			T257	26		T75	22		T258	22
auto[0]	values[4]	values[7]	36	1			T71	6		T259	14		T260	4
auto[0]	values[5]	values[0]	26	1			T68	26		-	-		-	-
auto[0]	values[5]	values[1]	64	1			T46	8		T261	2		T262	24
auto[0]	values[5]	values[2]	34	1			T87	2		T263	32		-	-
auto[0]	values[5]	values[3]	84	1			T43	10		T96	18		T264	18
auto[0]	values[5]	values[4]	66	1			T265	20		T266	8		T267	6
auto[0]	values[5]	values[5]	36	1			T91	8		T56	8		T268	12
auto[0]	values[5]	values[6]	54	1			T269	16		T270	2		T271	36
auto[0]	values[5]	values[7]	44	1			T272	6		T273	2		T274	24
auto[0]	values[6]	values[0]	24	1			T8	6		T57	8		T275	10
auto[0]	values[6]	values[1]	28	1			T276	8		T277	14		T278	6
auto[0]	values[6]	values[2]	68	1			T279	6		T83	28		T280	12
auto[0]	values[6]	values[3]	16	1			T70	16		-	-		-	-
auto[0]	values[6]	values[4]	20	1			T194	10		T281	10		-	-
auto[0]	values[6]	values[5]	48	1			T44	12		T282	22		T283	4
auto[0]	values[6]	values[6]	62	1			T190	2		T284	26		T285	8
auto[0]	values[6]	values[7]	24	1			T286	24		-	-		-	-
auto[0]	values[7]	values[0]	50	1			T5	22		T72	18		T287	2
auto[0]	values[7]	values[1]	8	1			T288	8		-	-		-	-
auto[0]	values[7]	values[2]	90	1			T7	6		T73	26		T289	32
auto[0]	values[7]	values[3]	38	1			T27	4		T290	14		T61	8
auto[0]	values[7]	values[4]	50	1			T193	14		T291	24		T292	12
auto[0]	values[7]	values[5]	10	1			T293	2		T294	8		-	-
auto[0]	values[7]	values[6]	54	1			T119	14		T92	12		T295	8
auto[0]	values[7]	values[7]	74	1			T196	4		T296	10		T297	30
auto[1]	values[0]	values[3]	2	1			T298	2		-	-		-	-
auto[1]	values[2]	values[0]	6	1			T224	6		-	-		-	-
auto[1]	values[2]	values[2]	4	1			T80	4		-	-		-	-
auto[1]	values[2]	values[7]	2	1			T77	2		-	-		-	-
auto[1]	values[3]	values[3]	2	1			T78	2		-	-		-	-
auto[1]	values[3]	values[6]	4	1			T246	4		-	-		-	-
auto[1]	values[4]	values[1]	8	1			T76	8		-	-		-	-
auto[1]	values[4]	values[4]	2	1			T79	2		-	-		-	-
auto[1]	values[4]	values[6]	4	1			T75	4		-	-		-	-
auto[1]	values[4]	values[7]	2	1			T71	2		-	-		-	-
auto[1]	values[5]	values[1]	2	1			T299	2		-	-		-	-
auto[1]	values[6]	values[3]	2	1			T70	2		-	-		-	-
auto[1]	values[7]	values[0]	2	1			T5	2		-	-		-	-
auto[1]	values[7]	values[3]	2	1			T81	2		-	-		-	-
auto[1]	values[7]	values[6]	2	1			T300	2		-	-		-	-