Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1469

1

T1

8

T14

22

T16

3

auto[1]

1482

1

T1

6

T14

12

T16

12

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

661

1

T16

15

T17

17

T62

25

auto[1]

2290

1

T1

14

T14

34

T17

9

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2696

1

T1

14

T14

34

T16

13

auto[1]

255

1

T16

2

T17

2

T62

8

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	570	1			T14	8		T16	4		T17	8
valid[1]	550	1			T1	1		T14	6		T16	5
valid[2]	615	1			T1	4		T14	9		T16	2
valid[3]	595	1			T1	3		T14	3		T16	1
valid[4]	621	1			T1	6		T14	8		T16	3

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	36	1			T17	2		T62	2		T63	1
auto[0]	auto[0]	valid[0]	auto[1]	218	1			T14	5		T17	2		T18	2
auto[0]	auto[0]	valid[1]	auto[0]	37	1			T17	2		T62	1		T65	1
auto[0]	auto[0]	valid[1]	auto[1]	236	1			T1	1		T14	5		T17	2
auto[0]	auto[0]	valid[2]	auto[0]	48	1			T16	1		T17	4		T62	3
auto[0]	auto[0]	valid[2]	auto[1]	233	1			T1	2		T14	7		T17	1
auto[0]	auto[0]	valid[3]	auto[0]	37	1			T107	2		T405	1		T108	2
auto[0]	auto[0]	valid[3]	auto[1]	222	1			T1	1		T14	2		T18	6
auto[0]	auto[0]	valid[4]	auto[0]	44	1			T16	2		T17	1		T62	2
auto[0]	auto[0]	valid[4]	auto[1]	231	1			T1	4		T14	3		T18	1
auto[0]	auto[1]	valid[0]	auto[0]	43	1			T16	4		T17	3		T139	1
auto[0]	auto[1]	valid[0]	auto[1]	222	1			T14	3		T18	5		T21	3
auto[0]	auto[1]	valid[1]	auto[0]	44	1			T16	5		T62	4		T88	1
auto[0]	auto[1]	valid[1]	auto[1]	193	1			T14	1		T18	2		T21	2
auto[0]	auto[1]	valid[2]	auto[0]	45	1			T16	1		T62	1		T63	1
auto[0]	auto[1]	valid[2]	auto[1]	244	1			T1	2		T14	2		T17	1
auto[0]	auto[1]	valid[3]	auto[0]	41	1			T17	1		T62	4		T107	2
auto[0]	auto[1]	valid[3]	auto[1]	228	1			T1	2		T14	1		T17	1
auto[0]	auto[1]	valid[4]	auto[0]	31	1			T17	2		T107	1		T108	1
auto[0]	auto[1]	valid[4]	auto[1]	263	1			T1	2		T14	5		T17	2
auto[1]	auto[0]	valid[0]	auto[0]	27	1			T62	2		T64	1		T139	1
auto[1]	auto[0]	valid[1]	auto[0]	20	1			T62	1		T107	2		T108	1
auto[1]	auto[0]	valid[2]	auto[0]	23	1			T107	1		T411	1		T24	1
auto[1]	auto[0]	valid[3]	auto[0]	29	1			T64	1		T107	1		T24	1
auto[1]	auto[0]	valid[4]	auto[0]	28	1			T62	3		T63	2		T64	1
auto[1]	auto[1]	valid[0]	auto[0]	24	1			T17	1		T88	1		T396	1
auto[1]	auto[1]	valid[1]	auto[0]	20	1			T396	3		T394	1		T386	1
auto[1]	auto[1]	valid[2]	auto[0]	22	1			T63	1		T107	1		T108	2
auto[1]	auto[1]	valid[3]	auto[0]	38	1			T16	1		T62	1		T63	2
auto[1]	auto[1]	valid[4]	auto[0]	24	1			T16	1		T17	1		T62	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal