Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17508

1

T2

5

T15

7

T16

424

auto[1]

22617

1

T1

14

T14

436

T17

84

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33596

1

T1

14

T2

4

T14

436

auto[1]

6529

1

T2

1

T15

5

T16

151

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	20624	1			T1	14		T2	2		T14	225
others[1]	3350	1			T14	39		T16	34		T17	78
others[2]	3447	1			T2	1		T14	31		T15	2
others[3]	3898	1			T14	47		T16	30		T17	65
interest[1]	2189	1			T2	1		T14	21		T16	26
interest[4]	13765	1			T1	14		T2	2		T14	148
interest[64]	6617	1			T2	1		T14	73		T15	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	5536	1			T2	1		T15	1		T16	153
auto[0]	auto[0]	others[1]	956	1			T16	22		T17	47		T62	26
auto[0]	auto[0]	others[2]	1000	1			T2	1		T16	28		T17	26
auto[0]	auto[0]	others[3]	1077	1			T16	20		T17	37		T62	49
auto[0]	auto[0]	interest[1]	632	1			T2	1		T16	17		T17	19
auto[0]	auto[0]	interest[4]	3659	1			T2	1		T15	1		T16	103
auto[0]	auto[0]	interest[64]	1778	1			T2	1		T15	1		T16	33
auto[0]	auto[1]	others[0]	11792	1			T1	14		T14	225		T17	41
auto[0]	auto[1]	others[1]	1844	1			T14	39		T17	10		T18	50
auto[0]	auto[1]	others[2]	1908	1			T14	31		T17	6		T18	28
auto[0]	auto[1]	others[3]	2208	1			T14	47		T17	10		T18	39
auto[0]	auto[1]	interest[1]	1193	1			T14	21		T17	5		T18	20
auto[0]	auto[1]	interest[4]	7955	1			T1	14		T14	148		T17	27
auto[0]	auto[1]	interest[64]	3672	1			T14	73		T17	12		T18	67
auto[1]	auto[0]	others[0]	3296	1			T2	1		T15	3		T16	84
auto[1]	auto[0]	others[1]	550	1			T16	12		T17	21		T62	16
auto[1]	auto[0]	others[2]	539	1			T15	2		T16	17		T17	12
auto[1]	auto[0]	others[3]	613	1			T16	10		T17	18		T62	15
auto[1]	auto[0]	interest[1]	364	1			T16	9		T17	16		T62	13
auto[1]	auto[0]	interest[4]	2151	1			T2	1		T15	2		T16	55
auto[1]	auto[0]	interest[64]	1167	1			T16	19		T17	36		T62	37

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal