Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	519	1			T33	10		T24	14		T41	8
all_values[1]	519	1			T33	10		T24	14		T41	8
all_values[2]	519	1			T33	10		T24	14		T41	8
all_values[3]	519	1			T33	10		T24	14		T41	8
all_values[4]	519	1			T33	10		T24	14		T41	8
all_values[5]	519	1			T33	10		T24	14		T41	8
all_values[6]	519	1			T33	10		T24	14		T41	8
all_values[7]	519	1			T33	10		T24	14		T41	8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2240

1

T33

51

T24

69

T41

35

auto[1]

1912

1

T33

29

T24

43

T41

29

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1683

1

T33

34

T24

52

T41

34

auto[1]

2469

1

T33

46

T24

60

T41

30

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2389

1

T33

45

T24

67

T41

42

auto[1]

1763

1

T33

35

T24

45

T41

22

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	105	1			T24	2		T41	2		T34	2
all_values[0]	auto[0]	auto[0]	auto[1]	52	1			T33	1		T24	1		T41	1
all_values[0]	auto[0]	auto[1]	auto[0]	91	1			T24	4		T41	2		T34	4
all_values[0]	auto[0]	auto[1]	auto[1]	47	1			T33	1		T24	1		T34	2
all_values[0]	auto[1]	auto[0]	auto[1]	125	1			T33	3		T24	4		T41	2
all_values[0]	auto[1]	auto[1]	auto[1]	99	1			T33	5		T24	2		T41	1
all_values[1]	auto[0]	auto[0]	auto[0]	110	1			T33	4		T24	4		T41	1
all_values[1]	auto[0]	auto[0]	auto[1]	54	1			T24	2		T41	1		T174	5
all_values[1]	auto[0]	auto[1]	auto[0]	97	1			T33	3		T24	3		T41	3
all_values[1]	auto[0]	auto[1]	auto[1]	49	1			T34	3		T174	1		T360	2
all_values[1]	auto[1]	auto[0]	auto[1]	114	1			T33	2		T24	3		T41	2
all_values[1]	auto[1]	auto[1]	auto[1]	95	1			T33	1		T24	2		T41	1
all_values[2]	auto[0]	auto[0]	auto[0]	109	1			T33	2		T24	1		T41	2
all_values[2]	auto[0]	auto[0]	auto[1]	53	1			T33	2		T24	2		T41	1
all_values[2]	auto[0]	auto[1]	auto[0]	76	1			T24	2		T41	1		T34	1
all_values[2]	auto[0]	auto[1]	auto[1]	41	1			T24	3		T34	1		T174	2
all_values[2]	auto[1]	auto[0]	auto[1]	135	1			T33	4		T24	4		T41	2
all_values[2]	auto[1]	auto[1]	auto[1]	105	1			T33	2		T24	2		T41	2
all_values[3]	auto[0]	auto[0]	auto[0]	106	1			T33	3		T24	5		T41	2
all_values[3]	auto[0]	auto[0]	auto[1]	38	1			T33	2		T41	1		T34	2
all_values[3]	auto[0]	auto[1]	auto[0]	96	1			T24	3		T41	4		T34	1
all_values[3]	auto[0]	auto[1]	auto[1]	56	1			T34	5		T174	2		T360	2
all_values[3]	auto[1]	auto[0]	auto[1]	126	1			T33	3		T24	5		T41	1
all_values[3]	auto[1]	auto[1]	auto[1]	97	1			T33	2		T24	1		T34	4
all_values[4]	auto[0]	auto[0]	auto[0]	101	1			T33	2		T24	5		T41	3
all_values[4]	auto[0]	auto[0]	auto[1]	59	1			T33	1		T24	2		T41	1
all_values[4]	auto[0]	auto[1]	auto[0]	86	1			T33	2		T24	1		T41	1
all_values[4]	auto[0]	auto[1]	auto[1]	54	1			T33	1		T24	1		T174	3
all_values[4]	auto[1]	auto[0]	auto[1]	109	1			T24	3		T41	2		T34	3
all_values[4]	auto[1]	auto[1]	auto[1]	110	1			T33	4		T24	2		T41	1
all_values[5]	auto[0]	auto[0]	auto[0]	148	1			T33	4		T24	3		T41	1
all_values[5]	auto[0]	auto[1]	auto[0]	155	1			T33	4		T24	3		T41	3
all_values[5]	auto[1]	auto[0]	auto[1]	111	1			T33	1		T24	6		T41	2
all_values[5]	auto[1]	auto[1]	auto[1]	105	1			T33	1		T24	2		T41	2
all_values[6]	auto[0]	auto[0]	auto[0]	112	1			T33	4		T24	5		T41	3
all_values[6]	auto[0]	auto[0]	auto[1]	53	1			T24	1		T41	1		T174	4
all_values[6]	auto[0]	auto[1]	auto[0]	97	1			T33	2		T24	4		T41	3
all_values[6]	auto[0]	auto[1]	auto[1]	49	1			T34	2		T174	3		T176	4
all_values[6]	auto[1]	auto[0]	auto[1]	119	1			T33	4		T24	3		T34	3
all_values[6]	auto[1]	auto[1]	auto[1]	89	1			T24	1		T41	1		T34	4
all_values[7]	auto[0]	auto[0]	auto[0]	119	1			T33	3		T24	5		T41	3
all_values[7]	auto[0]	auto[0]	auto[1]	57	1			T33	3		T24	1		T34	1
all_values[7]	auto[0]	auto[1]	auto[0]	75	1			T33	1		T24	2		T34	1
all_values[7]	auto[0]	auto[1]	auto[1]	44	1			T24	1		T41	2		T34	2
all_values[7]	auto[1]	auto[0]	auto[1]	125	1			T33	3		T24	2		T41	1
all_values[7]	auto[1]	auto[1]	auto[1]	99	1			T24	3		T41	2		T34	5

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal