Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	276789	1			T1	1		T2	15		T7	1
all_values[1]	276789	1			T1	1		T2	15		T7	1
all_values[2]	276789	1			T1	1		T2	15		T7	1
all_values[3]	276789	1			T1	1		T2	15		T7	1
all_values[4]	276789	1			T1	1		T2	15		T7	1
all_values[5]	276789	1			T1	1		T2	15		T7	1
all_values[6]	276789	1			T1	1		T2	15		T7	1
all_values[7]	276789	1			T1	1		T2	15		T7	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2212115

1

T1

8

T2

59

T7

8

auto[1]

2197

1

T2

61

T34

87

T41

45

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2212267

1

T1

8

T2

87

T7

8

auto[1]

2045

1

T2

33

T17

2

T64

1

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	276426	1			T1	1		T2	2		T7	1
all_values[0]	auto[0]	auto[1]	103	1			T2	6		T34	3		T41	3
all_values[0]	auto[1]	auto[0]	151	1			T2	7		T34	6		T41	1
all_values[0]	auto[1]	auto[1]	109	1			T34	5		T40	9		T360	2
all_values[1]	auto[0]	auto[0]	276412	1			T1	1		T2	7		T7	1
all_values[1]	auto[0]	auto[1]	112	1			T2	1		T34	9		T41	1
all_values[1]	auto[1]	auto[0]	147	1			T2	2		T34	2		T41	5
all_values[1]	auto[1]	auto[1]	118	1			T2	5		T34	1		T41	4
all_values[2]	auto[0]	auto[0]	276401	1			T1	1		T2	1		T7	1
all_values[2]	auto[0]	auto[1]	114	1			T2	2		T34	4		T41	3
all_values[2]	auto[1]	auto[0]	166	1			T2	10		T34	11		T41	1
all_values[2]	auto[1]	auto[1]	108	1			T2	2		T34	7		T41	2
all_values[3]	auto[0]	auto[0]	276383	1			T1	1		T2	11		T7	1
all_values[3]	auto[0]	auto[1]	139	1			T2	1		T34	10		T319	5
all_values[3]	auto[1]	auto[0]	156	1			T2	2		T34	3		T41	1
all_values[3]	auto[1]	auto[1]	111	1			T2	1		T34	4		T41	1
all_values[4]	auto[0]	auto[0]	276385	1			T1	1		T2	8		T7	1
all_values[4]	auto[0]	auto[1]	110	1			T34	4		T369	5		T41	5
all_values[4]	auto[1]	auto[0]	157	1			T2	4		T34	7		T40	6
all_values[4]	auto[1]	auto[1]	137	1			T2	3		T34	8		T41	1
all_values[5]	auto[0]	auto[0]	276198	1			T1	1		T2	4		T7	1
all_values[5]	auto[0]	auto[1]	319	1			T2	3		T17	2		T64	1
all_values[5]	auto[1]	auto[0]	161	1			T2	7		T34	6		T41	7
all_values[5]	auto[1]	auto[1]	111	1			T2	1		T34	3		T41	3
all_values[6]	auto[0]	auto[0]	276380	1			T1	1		T2	9		T7	1
all_values[6]	auto[0]	auto[1]	117	1			T34	3		T41	1		T40	7
all_values[6]	auto[1]	auto[0]	183	1			T2	3		T34	2		T41	8
all_values[6]	auto[1]	auto[1]	109	1			T2	3		T34	10		T41	2
all_values[7]	auto[0]	auto[0]	276400	1			T1	1		T2	4		T7	1
all_values[7]	auto[0]	auto[1]	116	1			T34	1		T41	1		T40	7
all_values[7]	auto[1]	auto[0]	161	1			T2	6		T34	6		T41	7
all_values[7]	auto[1]	auto[1]	112	1			T2	5		T34	6		T41	2