Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
72.13	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	1	37	97.37
Crosses	84	33	51	60.71

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	1	1	50.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	28	20	41.67	100	1	1	0
cr_modeXdummyXnum_lanes	36	5	31	86.11	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	977	1			T7	2		T5	4		T6	18
auto[SpiFlashAddrCfg]	906	1			T5	4		T6	12		T9	2
auto[SpiFlashAddr3b]	1054	1			T5	8		T11	8		T46	4
auto[SpiFlashAddr4b]	818	1			T5	10		T9	2		T12	2

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2872

1

T5

26

T9

10

T12

6

auto[1]

883

1

T7

2

T6

30

T11

10

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1914

1

T7

2

T5

22

T6

24

auto[1]

1841

1

T5

4

T6

6

T9

2

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1375	1			T7	2		T5	10		T6	20
values[1]	93	1			T5	2		T44	2		T199	4
values[2]	193	1			T43	4		T44	2		T195	6
values[3]	169	1			T5	6		T44	4		T78	4
values[4]	143	1			T11	2		T46	2		T88	4
values[5]	233	1			T5	2		T195	2		T90	4
values[6]	196	1			T5	4		T12	4		T46	4
values[7]	210	1			T6	2		T43	2		T44	4
values[8]	1143	1			T5	2		T6	8		T9	2

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3252

1

T7

2

T5

26

T6

30

auto[1]

503

1

T88

11

T89

5

T90

15

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

3636

1

T7

2

T5

26

T6

24

write

119

1

T6

6

T43

2

T72

2

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

1887

1

T5

12

T6

8

T9

2

valids[0x1]

1868

1

T7

2

T5

14

T6

22

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	194	1			T5	2		T11	2		T46	2
internal_process_ops[0x5a]	174	1			T5	2		T46	4		T73	2
internal_process_ops[0x05]	207	1			T9	6		T73	2		T43	2
internal_process_ops[0x35]	155	1			T195	4		T72	2		T74	4
internal_process_ops[0x15]	134	1			T7	2		T5	2		T6	2
internal_process_ops[0x03]	221	1			T12	2		T88	3		T195	2
internal_process_ops[0x0b]	211	1			T11	2		T49	2		T44	2
internal_process_ops[0x3b]	292	1			T5	4		T6	6		T12	2
internal_process_ops[0x6b]	292	1			T12	2		T120	6		T44	6
internal_process_ops[0xbb]	265	1			T46	4		T195	6		T79	6
internal_process_ops[0xeb]	247	1			T5	2		T9	2		T46	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3687

1

T7

2

T5

26

T6

24

auto[1]

68

1

T6

6

T74

2

T75

2

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_upload

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3755

1

T7

2

T5

26

T6

30

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	28	20	41.67	28
Automatically Generated Cross Bins	48	28	20	41.67	28
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Element holes

cp_is_flash	cp_is_write	cp_addr_mode	cp_addr_swap_en	cp_payload_swap_en	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[write]	*	[auto[0]]	[auto[1]]	--	--	4
[auto[0]]	[write]	*	[auto[1]]	[auto[0]]	--	--	4
[auto[1]]	[read]	[auto[SpiFlashAddrDisabled]]	*	[auto[0]]	--	--	2
[auto[1]]	[write]	[auto[SpiFlashAddrDisabled] , auto[SpiFlashAddrCfg]]	*	*	--	--	8
[auto[1]]	[write]	[auto[SpiFlashAddr3b]]	[auto[1]]	*	--	--	2
[auto[1]]	[write]	[auto[SpiFlashAddr4b]]	*	*	--	--	4

Uncovered bins

cp_is_flash	cp_is_write	cp_addr_mode	cp_addr_swap_en	cp_payload_swap_en	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[read]	[auto[SpiFlashAddrCfg] , auto[SpiFlashAddr3b] , auto[SpiFlashAddr4b]]	[auto[1]]	[auto[0]]	--	--	3
[auto[1]]	[write]	[auto[SpiFlashAddr3b]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

782

1

T5

4

T9

6

T46

2

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

179

1

T7

2

T6

14

T11

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

459

1

T5

4

T9

2

T12

4

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

222

1

T6

10

T73

2

T74

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

643

1

T5

8

T46

4

T43

10

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

231

1

T11

8

T73

4

T194

6

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

437

1

T5

10

T9

2

T12

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

183

1

T74

6

T75

2

T265

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

4

1

T61

4

-

-

-

-

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

12

1

T6

4

T74

2

T75

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

20

1

T43

2

T273

4

T304

10

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

20

1

T6

2

T83

4

T84

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

10

1

T72

2

T63

2

T305

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

10

1

T85

2

T303

2

T302

6

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

14

1

T279

6

T296

2

T273

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

26

1

T80

10

T55

2

T81

6

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

185

1

T88

7

T89

5

T90

8

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

157

1

T306

9

T307

4

T308

5

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

158

1

T88

4

T90

7

T307

7

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

3

1

T309

3

-

-

-

-

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	5	31	86.11	5

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[1]]	*	--	--	2

Uncovered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[1]]	[valids[0x0]]	0	1	1
[auto[1]]	[values[0]]	[valids[0x0]]	0	1	1
[auto[1]]	[values[4]]	[valids[0x1]]	0	1	1

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	306	1			T5	6		T73	2		T49	2
auto[0]	values[0]	valids[0x1]	1022	1			T7	2		T5	4		T6	20
auto[0]	values[1]	valids[0x1]	93	1			T5	2		T44	2		T199	4
auto[0]	values[2]	valids[0x0]	103	1			T43	4		T195	6		T200	2
auto[0]	values[2]	valids[0x1]	48	1			T44	2		T96	2		T196	2
auto[0]	values[3]	valids[0x0]	100	1			T44	4		T78	4		T72	2
auto[0]	values[3]	valids[0x1]	35	1			T5	6		T79	2		T238	4
auto[0]	values[4]	valids[0x0]	91	1			T46	2		T44	2		T47	6
auto[0]	values[4]	valids[0x1]	34	1			T11	2		T48	2		T219	2
auto[0]	values[5]	valids[0x0]	114	1			T195	2		T27	2		T265	2
auto[0]	values[5]	valids[0x1]	41	1			T5	2		T216	2		T74	4
auto[0]	values[6]	valids[0x0]	102	1			T5	4		T12	2		T46	4
auto[0]	values[6]	valids[0x1]	70	1			T12	2		T73	2		T43	2
auto[0]	values[7]	valids[0x0]	92	1			T43	2		T101	6		T191	4
auto[0]	values[7]	valids[0x1]	44	1			T6	2		T44	4		T45	2
auto[0]	values[8]	valids[0x0]	651	1			T5	2		T6	8		T9	2
auto[0]	values[8]	valids[0x1]	306	1			T11	2		T43	2		T78	8
auto[1]	values[0]	valids[0x1]	47	1			T88	3		T306	1		T308	3
auto[1]	values[2]	valids[0x0]	31	1			T310	5		T311	3		T312	3
auto[1]	values[2]	valids[0x1]	11	1			T313	1		T314	5		T315	3
auto[1]	values[3]	valids[0x0]	19	1			T309	5		T186	5		T314	4
auto[1]	values[3]	valids[0x1]	15	1			T306	3		T309	9		T316	3
auto[1]	values[4]	valids[0x0]	18	1			T88	4		T310	3		T317	4
auto[1]	values[5]	valids[0x0]	68	1			T90	4		T306	3		T307	7
auto[1]	values[5]	valids[0x1]	10	1			T318	10		-	-		-	-
auto[1]	values[6]	valids[0x0]	14	1			T319	5		T320	3		T312	3
auto[1]	values[6]	valids[0x1]	10	1			T90	3		T309	7		-	-
auto[1]	values[7]	valids[0x0]	53	1			T90	7		T321	4		T308	6
auto[1]	values[7]	valids[0x1]	21	1			T321	1		T317	5		T322	5
auto[1]	values[8]	valids[0x0]	125	1			T88	4		T89	5		T306	3
auto[1]	values[8]	valids[0x1]	61	1			T90	1		T308	2		T310	3