Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg
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Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
36.36 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv


Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 16 2 14 87.50
Crosses 72 54 18 25.00


Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_busy_bit 2 1 1 50.00 100 1 1 2
cp_is_host_read 2 0 2 100.00 100 1 1 2
cp_other_status 8 0 8 100.00 100 1 1 8
cp_sw_read_while_csb_active 2 0 2 100.00 100 1 1 2
cp_wel_bit 2 1 1 50.00 100 1 1 2


Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all_except_csb 64 48 16 25.00 100 1 1 0
cr_busyXwelXcsb 8 6 2 25.00 100 1 1 0


Summary for Variable cp_busy_bit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_busy_bit

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1711243 1 T7 1 T5 1 T6 1


Summary for Variable cp_is_host_read

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_is_host_read

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1591878 1 T7 1 T5 1 T6 1
auto[1] 119365 1 T43 14 T44 778 T45 6168


Summary for Variable cp_other_status

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 8 0 8 100.00


Automatically Generated Bins for cp_other_status

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:524287] 392656 1 T7 1 T5 1 T6 1
auto[524288:1048575] 184816 1 T46 676 T88 2359 T108 104
auto[1048576:1572863] 191092 1 T46 1 T88 981 T108 64
auto[1572864:2097151] 180820 1 T12 3673 T46 1546 T88 3719
auto[2097152:2621439] 196286 1 T46 749 T88 705 T49 569
auto[2621440:3145727] 171655 1 T46 2905 T88 3426 T108 38
auto[3145728:3670015] 168743 1 T46 1619 T88 202 T49 1
auto[3670016:4194303] 225175 1 T12 4515 T46 1228 T108 100


Summary for Variable cp_sw_read_while_csb_active

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_sw_read_while_csb_active

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 132556 1 T7 1 T5 1 T6 1
auto[1] 1578687 1 T12 9319 T46 8846 T88 13789


Summary for Variable cp_wel_bit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_wel_bit

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1711243 1 T7 1 T5 1 T6 1


Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 48 16 25.00 48


Automatically Generated Cross Bins for cr_all_except_csb

Element holes
cp_busy_bitcp_wel_bitcp_other_statuscp_is_host_readCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[1]] * * -- -- 16
[auto[1]] * * * -- -- 32


Covered bins
cp_busy_bitcp_wel_bitcp_other_statuscp_is_host_readCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0:524287] auto[0] 298548 1 T7 1 T5 1 T6 1
auto[0] auto[0] auto[0:524287] auto[1] 94108 1 T43 14 T44 778 T45 6168
auto[0] auto[0] auto[524288:1048575] auto[0] 183081 1 T46 676 T88 2359 T108 104
auto[0] auto[0] auto[524288:1048575] auto[1] 1735 1 T187 257 T188 65 T58 1
auto[0] auto[0] auto[1048576:1572863] auto[0] 186793 1 T46 1 T88 981 T108 64
auto[0] auto[0] auto[1048576:1572863] auto[1] 4299 1 T97 6 T187 1 T189 13
auto[0] auto[0] auto[1572864:2097151] auto[0] 175712 1 T12 3673 T46 1546 T88 3719
auto[0] auto[0] auto[1572864:2097151] auto[1] 5108 1 T187 255 T58 1 T190 7
auto[0] auto[0] auto[2097152:2621439] auto[0] 191743 1 T46 749 T88 705 T49 569
auto[0] auto[0] auto[2097152:2621439] auto[1] 4543 1 T97 116 T58 3 T189 10
auto[0] auto[0] auto[2621440:3145727] auto[0] 167167 1 T46 2905 T88 3426 T108 38
auto[0] auto[0] auto[2621440:3145727] auto[1] 4488 1 T97 4 T191 507 T189 722
auto[0] auto[0] auto[3145728:3670015] auto[0] 165513 1 T46 1619 T88 202 T49 1
auto[0] auto[0] auto[3145728:3670015] auto[1] 3230 1 T97 113 T188 1 T189 5
auto[0] auto[0] auto[3670016:4194303] auto[0] 223321 1 T12 4515 T46 1228 T108 100
auto[0] auto[0] auto[3670016:4194303] auto[1] 1854 1 T191 131 T189 90 T192 2


Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 6 2 25.00 6


Automatically Generated Cross Bins for cr_busyXwelXcsb

Element holes
cp_busy_bitcp_wel_bitcp_sw_read_while_csb_activeCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[1]] * -- -- 2
[auto[1]] * * -- -- 4


Covered bins
cp_busy_bitcp_wel_bitcp_sw_read_while_csb_activeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] 132556 1 T7 1 T5 1 T6 1
auto[0] auto[0] auto[1] 1578687 1 T12 9319 T46 8846 T88 13789

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