Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
78.08	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	32	96	75.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	32	96	75.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2369

1

T5

26

T9

10

T12

6

auto[1]

883

1

T7

2

T6

30

T11

10

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	304	1			T9	10		T120	6		T195	24
values[1]	232	1			T96	2		T26	18		T116	8
values[2]	448	1			T5	26		T44	34		T196	14
values[3]	462	1			T73	10		T47	10		T200	10
values[4]	418	1			T12	6		T127	12		T78	16
values[5]	530	1			T6	30		T194	6		T75	18
values[6]	378	1			T49	4		T43	26		T199	12
values[7]	480	1			T7	2		T11	10		T46	12

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	538	1			T5	26		T120	6		T44	34
values[1]	446	1			T7	2		T46	12		T199	12
values[2]	342	1			T11	10		T23	12		T116	8
values[3]	478	1			T12	6		T43	26		T127	12
values[4]	232	1			T49	4		T257	2		T236	14
values[5]	498	1			T6	30		T194	6		T47	10
values[6]	312	1			T9	10		T193	2		T197	14
values[7]	406	1			T73	10		T79	22		T294	10

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	32	96	75.00	32

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[values[2]]	0	1	1
[auto[0]]	[values[2]]	[values[4] , values[5]]	--	--	2
[auto[0]]	[values[4]]	[values[6]]	0	1	1
[auto[1]]	[values[0]]	[values[1] , values[2]]	--	--	2
[auto[1]]	[values[0]]	[values[4]]	0	1	1
[auto[1]]	[values[0]]	[values[6] , values[7]]	--	--	2
[auto[1]]	[values[1]]	[values[1]]	0	1	1
[auto[1]]	[values[1]]	[values[3] , values[4] , values[5] , values[6]]	--	--	4
[auto[1]]	[values[2]]	[values[4]]	0	1	1
[auto[1]]	[values[3]]	[values[0] , values[1] , values[2]]	--	--	3
[auto[1]]	[values[3]]	[values[4]]	0	1	1
[auto[1]]	[values[4]]	[values[1]]	0	1	1
[auto[1]]	[values[4]]	[values[4] , values[5] , values[6]]	--	--	3
[auto[1]]	[values[5]]	[values[1]]	0	1	1
[auto[1]]	[values[5]]	[values[4]]	0	1	1
[auto[1]]	[values[5]]	[values[6]]	0	1	1
[auto[1]]	[values[6]]	[values[0]]	0	1	1
[auto[1]]	[values[6]]	[values[2]]	0	1	1
[auto[1]]	[values[6]]	[values[6] , values[7]]	--	--	2
[auto[1]]	[values[7]]	[values[4] , values[5]]	--	--	2

Covered bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	100	1			T120	6		T195	24		T198	18
auto[0]	values[0]	values[1]	48	1			T27	30		T187	18		-	-
auto[0]	values[0]	values[3]	20	1			T72	10		T28	10		-	-
auto[0]	values[0]	values[4]	10	1			T249	2		T272	8		-	-
auto[0]	values[0]	values[5]	2	1			T233	2		-	-		-	-
auto[0]	values[0]	values[6]	24	1			T9	10		T323	2		T324	12
auto[0]	values[0]	values[7]	40	1			T294	10		T201	6		T285	6
auto[0]	values[1]	values[0]	6	1			T96	2		T292	4		-	-
auto[0]	values[1]	values[1]	34	1			T276	30		T325	4		-	-
auto[0]	values[1]	values[2]	12	1			T116	8		T326	4		-	-
auto[0]	values[1]	values[3]	6	1			T102	6		-	-		-	-
auto[0]	values[1]	values[4]	66	1			T236	14		T258	32		T86	4
auto[0]	values[1]	values[5]	18	1			T26	18		-	-		-	-
auto[0]	values[1]	values[6]	30	1			T234	12		T184	14		T327	4
auto[0]	values[1]	values[7]	10	1			T328	10		-	-		-	-
auto[0]	values[2]	values[0]	74	1			T5	26		T44	34		T329	6
auto[0]	values[2]	values[1]	52	1			T196	14		T300	2		T203	36
auto[0]	values[2]	values[2]	50	1			T24	4		T280	18		T288	10
auto[0]	values[2]	values[3]	14	1			T219	14		-	-		-	-
auto[0]	values[2]	values[6]	6	1			T330	2		T331	4		-	-
auto[0]	values[2]	values[7]	32	1			T332	26		T252	6		-	-
auto[0]	values[3]	values[0]	20	1			T238	20		-	-		-	-
auto[0]	values[3]	values[1]	42	1			T178	22		T333	20		-	-
auto[0]	values[3]	values[2]	84	1			T267	20		T210	8		T8	30
auto[0]	values[3]	values[3]	18	1			T256	8		T63	8		T334	2
auto[0]	values[3]	values[4]	32	1			T190	20		T335	12		-	-
auto[0]	values[3]	values[5]	68	1			T47	10		T200	10		T266	22
auto[0]	values[3]	values[6]	56	1			T193	2		T197	14		T239	10
auto[0]	values[3]	values[7]	30	1			T275	2		T336	18		T337	10
auto[0]	values[4]	values[0]	47	1			T78	16		T103	14		T93	13
auto[0]	values[4]	values[1]	70	1			T45	18		T216	18		T58	20
auto[0]	values[4]	values[2]	6	1			T274	6		-	-		-	-
auto[0]	values[4]	values[3]	86	1			T12	6		T127	12		T338	6
auto[0]	values[4]	values[4]	22	1			T339	10		T340	6		T269	6
auto[0]	values[4]	values[5]	60	1			T297	4		T341	16		T205	6
auto[0]	values[4]	values[7]	76	1			T79	22		T273	38		T342	16
auto[0]	values[5]	values[0]	46	1			T240	6		T223	12		T343	2
auto[0]	values[5]	values[1]	22	1			T296	14		T211	6		T289	2
auto[0]	values[5]	values[2]	22	1			T278	16		T247	6		-	-
auto[0]	values[5]	values[3]	52	1			T344	14		T48	12		T250	26
auto[0]	values[5]	values[4]	60	1			T237	16		T220	10		T214	20
auto[0]	values[5]	values[5]	100	1			T29	26		T261	10		T253	28
auto[0]	values[5]	values[6]	44	1			T61	10		T345	4		T346	20
auto[0]	values[5]	values[7]	32	1			T101	12		T191	20		-	-
auto[0]	values[6]	values[0]	54	1			T293	22		T232	32		-	-
auto[0]	values[6]	values[1]	44	1			T199	12		T246	2		T286	16
auto[0]	values[6]	values[2]	38	1			T213	38		-	-		-	-
auto[0]	values[6]	values[3]	58	1			T43	26		T229	28		T347	4
auto[0]	values[6]	values[4]	4	1			T49	4		-	-		-	-
auto[0]	values[6]	values[5]	14	1			T348	2		T215	12		-	-
auto[0]	values[6]	values[6]	26	1			T304	26		-	-		-	-
auto[0]	values[6]	values[7]	16	1			T189	16		-	-		-	-
auto[0]	values[7]	values[0]	70	1			T130	18		T222	12		T349	14
auto[0]	values[7]	values[1]	28	1			T46	12		T350	16		-	-
auto[0]	values[7]	values[2]	90	1			T23	12		T282	10		T351	2
auto[0]	values[7]	values[3]	60	1			T97	16		T202	30		T268	14
auto[0]	values[7]	values[4]	12	1			T257	2		T228	6		T262	4
auto[0]	values[7]	values[5]	56	1			T25	14		T92	4		T94	2
auto[0]	values[7]	values[6]	20	1			T279	14		T226	6		-	-
auto[0]	values[7]	values[7]	30	1			T217	8		T212	10		T206	6
auto[1]	values[0]	values[0]	26	1			T224	26		-	-		-	-
auto[1]	values[0]	values[3]	20	1			T207	20		-	-		-	-
auto[1]	values[0]	values[5]	14	1			T295	14		-	-		-	-
auto[1]	values[1]	values[0]	24	1			T291	24		-	-		-	-
auto[1]	values[1]	values[2]	4	1			T299	4		-	-		-	-
auto[1]	values[1]	values[7]	22	1			T204	22		-	-		-	-
auto[1]	values[2]	values[0]	14	1			T290	14		-	-		-	-
auto[1]	values[2]	values[1]	54	1			T182	16		T218	38		-	-
auto[1]	values[2]	values[2]	6	1			T227	6		-	-		-	-
auto[1]	values[2]	values[3]	28	1			T352	28		-	-		-	-
auto[1]	values[2]	values[5]	58	1			T74	30		T260	24		T271	4
auto[1]	values[2]	values[6]	22	1			T287	22		-	-		-	-
auto[1]	values[2]	values[7]	38	1			T301	38		-	-		-	-
auto[1]	values[3]	values[3]	30	1			T77	30		-	-		-	-
auto[1]	values[3]	values[5]	16	1			T83	16		-	-		-	-
auto[1]	values[3]	values[6]	56	1			T84	32		T281	24		-	-
auto[1]	values[3]	values[7]	10	1			T73	10		-	-		-	-
auto[1]	values[4]	values[0]	15	1			T265	8		T93	7		-	-
auto[1]	values[4]	values[2]	10	1			T82	10		-	-		-	-
auto[1]	values[4]	values[3]	20	1			T353	16		T243	4		-	-
auto[1]	values[4]	values[7]	6	1			T354	6		-	-		-	-
auto[1]	values[5]	values[0]	12	1			T355	12		-	-		-	-
auto[1]	values[5]	values[2]	10	1			T356	10		-	-		-	-
auto[1]	values[5]	values[3]	30	1			T264	30		-	-		-	-
auto[1]	values[5]	values[5]	78	1			T6	30		T194	6		T75	18
auto[1]	values[5]	values[7]	22	1			T244	22		-	-		-	-
auto[1]	values[6]	values[1]	50	1			T81	28		T302	22		-	-
auto[1]	values[6]	values[3]	34	1			T85	8		T357	26		-	-
auto[1]	values[6]	values[4]	26	1			T180	18		T270	8		-	-
auto[1]	values[6]	values[5]	14	1			T230	14		-	-		-	-
auto[1]	values[7]	values[0]	30	1			T358	30		-	-		-	-
auto[1]	values[7]	values[1]	2	1			T7	2		-	-		-	-
auto[1]	values[7]	values[2]	10	1			T11	10		-	-		-	-
auto[1]	values[7]	values[3]	2	1			T359	2		-	-		-	-
auto[1]	values[7]	values[6]	28	1			T80	28		-	-		-	-
auto[1]	values[7]	values[7]	42	1			T55	24		T303	18		-	-