Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.26	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	2	58	96.67

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	2	58	96.67	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	84	1			T12	2		T46	6		T49	2
auto[ReadAddrCrossIntoMailbox]	30	1			T238	8		T178	8		T345	2
auto[ReadAddrCrossOutOfMailbox]	50	1			T12	2		T120	4		T193	2
auto[ReadAddrCrossAllMailbox]	62	1			T130	4		T300	2		T206	2
auto[ReadAddrOutsideMailbox]	775	1			T5	6		T6	6		T9	2

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

504

1

T5

3

T6

3

T9

1

auto[1]

497

1

T5

3

T6

3

T9

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	138	1			T12	2		T195	2		T130	6
read_ops[0x0b]	114	1			T11	2		T49	2		T44	2
read_ops[0x3b]	190	1			T5	4		T6	6		T12	2
read_ops[0x6b]	199	1			T12	2		T120	6		T44	6
read_ops[0xbb]	183	1			T46	4		T195	6		T79	6
read_ops[0xeb]	177	1			T5	2		T9	2		T46	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	2	58	96.67	2

Automatically Generated Cross Bins for cr_all

Element holes

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	NUMBER	STATUS
[read_ops[0x03]]	[auto[ReadAddrCrossIntoMailbox]]	*	--	--	2

Covered bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	2	1			T192	1		T361	1		-	-
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	2	1			T192	1		T361	1		-	-
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	4	1			T272	1		T234	1		T255	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	4	1			T272	1		T234	1		T255	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	2	1			T255	2		-	-		-	-
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	2	1			T255	2		-	-		-	-
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	61	1			T12	1		T195	1		T130	3
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	61	1			T12	1		T195	1		T130	3
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	4	1			T49	1		T238	1		T339	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	4	1			T49	1		T238	1		T339	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	2	1			T178	2		-	-		-	-
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	2	1			T178	2		-	-		-	-
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	1	1			T277	1		-	-		-	-
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	1	1			T277	1		-	-		-	-
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	1	1			T277	1		-	-		-	-
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	1	1			T277	1		-	-		-	-
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	50	1			T11	1		T44	1		T79	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	48	1			T11	1		T44	1		T79	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	9	1			T58	1		T274	1		T362	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	9	1			T58	1		T274	1		T362	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	4	1			T238	1		T178	1		T255	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	4	1			T238	1		T178	1		T255	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	7	1			T12	1		T193	1		T206	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	7	1			T12	1		T193	1		T206	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	8	1			T300	1		T206	1		T178	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	8	1			T300	1		T206	1		T178	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	68	1			T5	2		T6	3		T44	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	66	1			T5	2		T6	3		T44	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	12	1			T12	1		T120	1		T272	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	12	1			T12	1		T120	1		T272	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	1	1			T238	1		-	-		-	-
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	1	1			T238	1		-	-		-	-
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	5	1			T120	2		T238	1		T178	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	5	1			T120	2		T238	1		T178	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	4	1			T178	1		T274	1		T252	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	4	1			T178	1		T274	1		T252	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	78	1			T44	3		T195	1		T47	3
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	77	1			T44	3		T195	1		T47	3
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	8	1			T46	2		T191	2		T272	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	8	1			T46	2		T191	2		T272	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	2	1			T277	1		T363	1		-	-
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	2	1			T277	1		T363	1		-	-
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	3	1			T277	2		T363	1		-	-
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	3	1			T277	2		T363	1		-	-
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	7	1			T234	2		T178	1		T277	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	7	1			T234	2		T178	1		T277	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	72	1			T195	3		T79	3		T200	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	71	1			T195	3		T79	3		T200	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	7	1			T46	1		T130	1		T338	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	7	1			T46	1		T130	1		T338	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	6	1			T238	2		T178	1		T345	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	6	1			T238	2		T178	1		T345	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	5	1			T178	1		T259	1		T277	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	5	1			T178	1		T259	1		T277	2
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	9	1			T130	2		T364	1		T345	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	9	1			T130	2		T364	1		T345	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	62	1			T5	1		T9	1		T73	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	61	1			T5	1		T9	1		T73	1